Answers Database

VERILOG, NGD2VER: How to initialize RAM in Verilog functional and timing simulation


Record #2684

Product Family:  Software

Product Line:  Merged Core

Problem Title:
VERILOG, NGD2VER:  How to initialize RAM in Verilog functional and
timing simulation



Problem Description:
Keywords: Verilog, initialize, RAM, functional, timing,
simulation

Urgency: standard

General Description:

Is there a way to initialize the RAMs in a Verilog functional
or timing simulation so that they come up in a defined
state prior to being written to?


Solution 1:


Functional Simulation:
---------------------
RAM initialization is not done for you automatically
in M1.3 for either Verilog simulation of Concept designs, or
behavioral simulation of Verilog designs in Synopsys.

In M1.4, it will be supported for both Concept functional
simulation after running concept2xil (Unified library
functional simulation) and Verilog simulation after NGDBUILD
if you attach an INIT property to the RAM.

To do it manually, say you have a ram32x1s RAM in your .v file:


  ram32x1s I27_1 (.o(QOUT), .d(DIN_I), .we(WE_IN), .a4(A4),
     .a1(A1), .a3(A3), .a2(A2), .a0(A0),
     .wclk(_XSIGRAMSWCLK0));

You would need to manually initialize the RAM doing the same
thing that is done by NGD2VER in the timing simulation
netlist:

1. Declare a dummy bit vector reg for the RAM:

   reg [0:31] I27_1_mem;

2. Next, initialize it as follows in a separate initial block:

  initial
  begin
    I27  I27_1_mem = 32'h00000000; // load I27_1 RAM
    I27_1.mem[0] = I27_1_mem[31];
    I27_1.mem[1] = I27_1_mem[30];
    I27_1.mem[2] = I27_1_mem[29];
    I27_1.mem[3] = I27_1_mem[28];
    I27_1.mem[4] = I27_1_mem[27];
    I27_1.mem[5] = I27_1_mem[26];
    I27_1.mem[6] = I27_1_mem[25];
    I27_1.mem[7] = I27_1_mem[24];
    I27_1.mem[8] = I27_1_mem[23];
    I27_1.mem[9] = I27_1_mem[22];
    I27_1.mem[10] = I27_1_mem[21];
    I27_1.mem[11] = I27_1_mem[20];
    I27_1.mem[12] = I27_1_mem[19];
    I27_1.mem[13] = I27_1_mem[18];
    I27_1.mem[14] = I27_1_mem[17];
    I27_1.mem[15] = I27_1_mem[16];
    I27_1.mem[16] = I27_1_mem[15];
    I27_1.mem[17] = I27_1_mem[14];
    I27_1.mem[18] = I27_1_mem[13];
    I27_1.mem[19] = I27_1_mem[12];
    I27_1.mem[20] = I27_1_mem[11];
    I27_1.mem[21] = I27_1_mem[10];
    I27_1.mem[22] = I27_1_mem[9];
    I27_1.mem[23] = I27_1_mem[8];
    I27_1.mem[24] = I27_1_mem[7];
    I27_1.mem[25] = I27_1_mem[6];
    I27_1.mem[26] = I27_1_mem[5];
    I27_1.mem[27] = I27_1_mem[4];
    I27_1.mem[28] = I27_1_mem[3];
    I27_1.mem[29] = I27_1_mem[2];
    I27_1.mem[30] = I27_1_mem[1];
    I27_1.mem[31] = I27_1_mem[0];
   end


Timing Simulation:
------------------
In M1.3, the initial values are assigned to the RAM by
NGD2VER in the design .v file.	NGD2VER declares the
dummy bit vector register for you, and also writes out
the value assignments for you as well.

This functionality is currently broken in M1.4.4, but should
be fixed in the full M1.4 release.






End of Record #2684