Answers Database

M1 CPLD: How to lock the pins on a CPLD (7300/9500)?


Record #2719

Product Family:  Software

Product Line:  CPLD Implementation

Problem Title:
M1 CPLD: How to lock the pins on a CPLD (7300/9500)?


Problem Description:
Keywords: pinout, pin locking, guide file, pin assignment, LOC

Urgency: standard

General Description:

How to control the pinout of a design with Pin assignments and
pin locking.


Solution 1:

Pinout controlled by Pin & Function Block Assignment:

A. Pin Assignment -

You can assign explicit locations for pins in your design using
the LOC attribute. To assign a pin location, apply the
following attribute to a pad symbol (IPAD, OPAD or IOPAD) in
your schematic:

LOC=pin_name

You can also use the UCF file to specify your LOC constraint. The
correct syntax is:

INST FRED LOC=pin_name;

For PC and PQ type packages, the pin_name takes the form "Pnn"
where nn is a number. For example, for the PC84 package, the
valid range for pin_name is P1 through P84. For grid array type
packages (PG and BG), the pin_name takes the form "rc", where r
is the row letter and c is the column number.

The LOC attribute cannot be applied to multi-bit pad components
such as OPAD8. You must use individual pad symbols in your
schematic if you want to perform pin assignment.

Whenever your design contains any LOC attributes, you should
specify the target device type using the Design Manager or the
schematic PART attribute. LOC attributes are not always
compatible when retargeting a design between different package
types, device types or device families. LOC attributes are
unconditional in that the software will not attempt to relocate
a pin if it cannot achieve the specified assignment. If you
specify a set of LOC attributes that the fitter cannot satisfy,
the fitter will terminate with an error.

LOC attributes override the pin assignments in the guide file
if you lock your pinout. This allows you to make explicit
changes to your committed pinout. If you override an assignment
in the guide file using LOC attributes, the software will issue
a warning. The fitter will then produce a new guide file
recording the modified pinout, provided the fitting is
successful.

If your objective is to preserve a previously created pinout,
Xilinx recommend you use the pinfreeze feature instead of
back-annotating the existing pinout into your design schematic
using the LOC attribute. The guide file saved from the previous
design implementation contains additional information to help
the fitter to successfully fit your modified design.

B. Function Block/Macrocell Assignment -

You can explicitly assign internal nodes in your design to
specific function blocks or even specific macrocells of the
target device. To assign an internal node to a specific
location, apply the following attribute to a symbol or its
output net:

LOC=FBnn[_mm]

where nn is a valid function block number and mm (optional) is
a valid macrocell number for the target device.

The correct UCF file syntax is:

INST FRED LOC=FBnn[_mm]; - For a symbol

AND/OR

NET JACK LOC=FBnn[_mm]; - For an output net



Solution 2:

Pinout chosen by the software:

When you first run the fitter before your pinout is committed,
the software automatically selects pin locations for your I/O
signals. Pin locations are selected which will give you the
greatest flexibility to iterate your design without having to
move any of the pins.

Xilinx strongly recommends that you allow the software to
automatically generate your initial pinout. Attempting to
select your own initial pin preferences reduces the ability of
the fitter to implement your design successfully the first
time. It further reduces the amount of logic changes you could
make after freezing your pinout.



Solution 3:

Pinout controlled by Pin Locking:

If you have successfully fit a design into a CPLD device and
you build a prototype containing the device, you will probably
want to "lock" the pinout. Each time the fitter successfully
implements your design, it creates a guide file
(design_name.gyd), which contains all the resulting pinout
information. After you commit your pinout, subsequent design
iterations cause the guide file to be read by the fitter and
your committed pinout will be preserved.

From the Design Manager, enter the Flow Engine. In
the Flow Engine go to the design implementation options through
Setup -> Options.

In the options dialog, Select down arrow adjacent to
Guide Design. This will display a list of versions and
revisions associated with the design. Select the previous
version and revision in which your desired pinout was
implemented and select OK. This will return you to the Flow
Engine. When you RUN the design through, the pinouts from the
selected revision will be used.



Solution 4:

Pin Assignment Precautions:

You can apply the LOC attribute to as many pad symbols in your
design as you like. However, each pin assignment further
constrains the software making it more difficult for the fitter
to automatically allocate logic and I/O resources for the
remaining I/O signals in your design.

When you manually assign output and I/O pins, you force the
software to place associated logic functions into specific
macrocells and specific function blocks. If the associated
logic does not exceed the available function block resources
(macrocells, product terms, and FastCONNECT inputs), the logic
is mapped into the macrocell and the design will route in the
FastCONNECT.

It is usually best to allow the fitter to automatically assign
most or all of the pins based on the most efficient placement
of logic in the device. The fitter automatically establishes a
pinout which best allows for future design iterations without
pin relocation. Any manual pin assignments you make in your
design may not allow as much tolerance for changes in the logic
associated with those pins, and in the logic physically mapped
to nearby locations in the device.

If you are assigning pin locations to signals used as clocks,
asynchronous set/reset, or output enable in your design, you
should assign them to the GCK, GSR and GTS pins on the device
if you want to take advantage of these global resources. The
fitter will still automatically assign other clock, set/reset
and output enable inputs to remaining GCK, GSR and GTS pins if
available.



Solution 5:

Ignoring the LOC Attribute:

If your schematic contains LOC attributes or if you are using
a UCF file to specify pin locations and you want to let the
fitter automatically assign all I/O pins, you can set the
fitter to ignore all LOC attributes. This allows you to
temporarily ignore all the LOC attributes in your schematic
and/or UCF file. This is useful if you want to test how your
design fits a different target device without removing all the
LOC attributes from your schematic.

Go to the Flow Engine from the Xilinx Design Manager and
select:

Setup -> Options

The Design Implementation Option menu appears. Select:

Edit Template

Then select the Fitting tab. Lastly, place a check in the box
adjacent to Ignore Design Assignments. Then click OK.



End of Record #2719