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Foundation F1.3/F1.4, XVHDL: I/O flip-flops not inferred by VHDL synthesizer


Record #2722

Product Family:  Software

Product Line:  Metamor

Problem Title:
Foundation F1.3/F1.4, XVHDL:  I/O flip-flops not inferred by VHDL
synthesizer



Problem Description:
Keywords:  XVHDL, Metamor, I/O flip-flops, ff, ifd, ifdx

Urgency:  Standard

General Description:

Versions of the XVHDL compiler which come with Foundation F1.x, do not infer I/O
 flip-flops.  However, described below are 2
ways you an specify their use in your design:

1) Use MAP to perform the equivalent function.
2) Instantiate them individually.


Solution 1:

With Foundation 6.x, XVHDL inferred I/O flip-flops where
appropriate.  However, with Foundation F1.x, XVHDL infers only
CLB flip-flops.  In order for flip-flops which are able to be
merged into IOBs to be used, the MAP program in the Implementation
phase of the design flow must be used.


The default MAP setting is NOT to merge flip-flops into the
IOBs.  To enable this option in MAP, a customized template is
required.

1.  From the Design Manager, select Utilities -> Template
    Manager

2. Select the New button and give your custom template a name.

3. Select your template from the Template window and press the
   customize button.

4. In the Program Name selection box, enter:  MAP.
   In the Program Options selection box, enter:

   -pr I, O, or B

   (Pack internal flops/latches into input (I), output (O),
    or both (B) types of IOB's)


5. Hit the OK button and exit the Template Manager by clicking
   the Close button.

6. When implementing the design, select your newly created
   template in the Implementation field of the Design
   Implementation Options window.



Solution 2:

Another approach is instantiation:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY METAMOR;
USE METAMOR.attributes.all;

ENTITY TEST IS
 PORT(clock		       : IN STD_LOGIC;
       mux_in			: IN STD_LOGIC;
       mux_out			: OUT STD_LOGIC);
  attribute inhibit_buf : boolean;
  attribute inhibit_buf of clock, mux_in: signal is true;
END TEST;

architecture INSIDE OF TEST IS

  COMPONENT bufg
  PORT(i		: IN STD_LOGIC;
       o		: OUT STD_LOGIC);
  END COMPONENT;

  COMPONENT ifdx1
  PORT(ce		: IN STD_LOGIC;
       c		: IN STD_LOGIC;
       d		: IN STD_LOGIC;
       q		: OUT STD_LOGIC);
  END COMPONENT;

  SIGNAL clock_s		: STD_LOGIC;

BEGIN
  u0 : bufg PORT MAP (i => clock, o => clock_s);
  u1 : ifdx1 PORT MAP ( ce => '0', c => clock_s, d => mux_in,
			q => mux_out);

end INSIDE;



End of Record #2722