Answers Database

FPGA Express/M1.3: HDL Simulation of HDL only designs synthesized with FPGA Express


Record #2734

Product Family:  Software

Product Line:  Synopsys

Problem Title:
FPGA Express/M1.3: HDL Simulation of HDL only designs synthesized with
FPGA Express



Problem Description:
keywords: simulation,HDL,VHDL,Verilog,FPGA Express, FPGA, Express

Urgency: standard

General Description:

FPGA Express is a synthesis only tool.	It is possible to perform functional
and timing simulation on design synthesized with FPGA Express.	This solution
record shows the steps to follow for HDL simulation of a purely HDL design,
which was synthesized with FPGA Express.


Solution 1:

Simulation Flows in M1.3

In the M1 design methodology, there are four possible simulation flows:

       Pre-synthesis RTL simulation(functional simulation)
       Post-synthesis pre-route simulation(post-translate simulation)
       Post-map pre-route simulation(post-map simulation
       Post-par simulation(timing simulation).


Each of these simulation flows adds greater accuracy the closer the design
is to becoming fully placed and routed. The advantage of having so many possible
 simulation points is to be able to check that the synthesis and
place and route tools are creating the desired design. By using the same
testbench and comparing the results at each of the simulation stages, a user
can be confident that what was synthesized and optimized is what was desired.

Pre-synthesis RTL simulation is traditionally known as functional simulation.
The main purpose of HDL functional simulation is to determine if the behavior
of the HDL is what is expected.  In the existing functional simulation flow
with Express, functional simulation is possible if the HDL code does not have
instantiated FFS, OBUF, or OBUFTs.  Instantiated FFS, OBUF, and OBUFTs have
extra pins for simulation of the GSR and GTS.  Instantiated combinational
logic, RAM/ROM primitives, or I/O combinational logic can be simulated.
Instantiated LogiBLOX can also be simulated by using the behaviorial model
produced by LogiBLOX.

Because FPGA Express is only a synthesis tool, the pre-synthesis RTL
simulation must be performed using a different HDL synthesis tool.

If there is no way to avoid instantiation of FFS, OBUF, or OBUFTs, then
another type of simulation should be used: Post-synthesis pre-route
simulation (post-ngdbuild).


Post-translate simulation is a simulation flow in M1.  Like pre-synthesis RTL
simulation, it is a functional simulation, but unlike pre-synthesis RTL
simulation, the behavior in this type of simulation is not based on the source
HDL.  With this type of flow, the synthesized logic behavior is evaluated.  It
does not matter if there are instantiated FFS, OBUF, or OBUFTs, since NGDBUILD
(translate) will convert all logic in the design to simulation primitives
(SIMPRIMS).  Logic converted to simprims can be simulated by the Xilinx Verilog
or VITAL simulation libraries.	The logic simulated in this flow has not been
trimmed.  Since it is possible that trimming of a design could change behavior,
in the M1 flow, there is flow to verify that logical trimming has not changed
the design behavior.


The third type of simulation possible in M1 is post-map pre-route simulation.
The M1 map’tool trims redundant logic from a design and maps logic to the
appropriate technology.  Simulating after a design is mapped lets a user
verify that the optimized and mapped design behavior is still consistent with
pre-synthesis RTL simulation and post-synthesis pre-route simulation.  Like
post-synthesis pre-route simulation, instantiated FFS, OBUF, or OBUFTs do not
make a difference, since all the logic in the design has already been
translated into SIMPRIMS.


The last type of simulation in the M1 flow is the traditional HDL timing
simulation.  Here all timing due to logic levels and routing is taken into
account, along with behavior of the trimmed and mapped logic.  Timing
information for a design is back-annotated into a SDF file.  Separation of
the timing information into an SDF file has several advantages:  timing
information separated into a SDF file allows the Xilinx design to be
simulated in a variety of 3rd party HDL simulators of choice; this also
allows for the increased speed of the timing simulation. Consult your HDL
simulator’s owner’s manual for more information on SDF features that the
simulator can use.



Solution 2:

Simulation of Modules/Black-Box Designs

In the FPGA Express v1.2 M1.3 design flow, it is possible to instantiate
black-box designs if Express is the top-level tool.  Black-Box/modules instantia
ted in Express are LogiBLOX modules, LogiCORE, or unified XNF files.
By definition, these instantiated modules cannot be simulated in the
pre-synthesis RTL simulation flow, except for LogiBLOX instantiations.
Pre-synthesis RTL simulation means that all behavior in the design is
described in the HDL code.  Instantiated LogiBLOX can be simulated
pre-synthesis RTL simulation, since the LogiBLOX tool can create behavioral
HDL models which can be used for pre-synthesis RTL simulation.	Instantiated
black-boxes without behavior, like an XNF file, can only be functionally
simulated post-ngdbuild.

Detailed Simulation Flows for FPGA Express v1.2 and M1.3


Pre-synthesis RTL Simulation

  1. Collect all HDL files for the design you wish to simulate.
  2. Create a testbench file.
  3. Read in HDL files and testbench files into the HDL simulation tool.

This flow is HDL functional simulation.  The specific procedures for this
flow will be dependent on the HDL simulator used.  Please consult your HDL
simulator documentation for more information.


Post-Synthesis pre-Route Simulation

  1. Synthesize HDL code in FPGA Express and create an XNF file.
  2. Run NGDBUILD (command line or via the Design Manager), with the XNF
     file(s) from Express along with any other files to create a .NGD file.
     If you are using the Design Manager, the‘translate’step will produce the
     .NGD file.
  3. Run NGD2VHDL or NGD2VER on the .NGD file produced by NGDBUILD.  Use the
     command-line options for NGD2VHDL or NGD2VER appropriate to your HDL
     simulator.  For more information on NGD2VHDL and NGD2VER, see Chapters
     17 and 18 of the Development System Reference Guide.
  4. With the behavioral .VHD or .V file created by NGD2VHDL or NGD2VER,
     combine these files with the testbench and simulate.


Post-Synthesis post-map simulation

  1. Synthesize HDL code in FPGA Express and create an XNF file.
  2. Run NGDBUILD (command line or via the Design Manager), with the XNF
     file(s) from Express along with any other files to create a .NGD file.
     If you are using the Design Manager, the‘translate’step will produce the
     .NGD file.
  3. Run MAP on the .NGD file to produce a .NCD file, a mapped design.
  4. Take the .NCD and .NGM files created by MAP, and provide these files as
     inputs to NGDANNO, which will produce a .NGA file.
  5. For a Verilog simulation flow, run NGD2VER on the .NGA file.
     For a VHDL simulation flow, run NGD2VHDL on the .NGA file.
     Use the command-line options relevant to the simulator to be used.
     An .SDF file will also be produced which only contains block delays.
     Use of the .SDF file is optional at this point, as no timing information
     is contained in this file yet.
  6. Using either the .V or .VHD file, produced by NGD2VER or NGD2VHDL,
     simulate with the testbench.


Post-synthesis post-route simulation

  1. Synthesize HDL code in FPGA Express and create an XNF file.
  2. Run NGDBUILD (command line or via the Design Manager), with the XNF
     file(s) from Express along with any other files to create a .NGD file.
     If you are using the Design Manager, the‘translate’step will produce the
     .NGD file.
  3. Run MAP on the .NGD file to produce a .NCD file, a mapped design.
  4. Run PAR on the .NCD file to produce a routed .NCD file.
  5. Take the .NCD file from PAR and the .NGM file from MAP, and provide
     these files as inputs to NGDANNO, which will produce a .NGA file.
  6. For a Verilog simulation flow, run NGD2VER on the .NGA file.
     For a VHDL simulation flow, run NGD2VHDL on the .NGA file.
     Use the command-line options relevant to the simulator to be used.
     An .SDF with full timing information will also be produced.
  7. Using either the .V or .VHD file, produced by NGD2VER or NGD2VHDL,
     simulate with the testbench and the .SDF file produced.



End of Record #2734