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Glossary of terms - programmable logic(CPLD, FPGA), ASIC etc.


Record #2736

Product Family:  Documentation

Product Line:  Other

Problem Title:
Glossary of terms - programmable logic(CPLD, FPGA), ASIC etc.


Problem Description:
Keywords:  programmable logic, CPLD, FPGA, ASIC, LUT, gate array, standard cell,
 sea of gates

Urgency: Standard


Solution 1:

Glossary of terms

ASIC:
Application Specific Integrated Circuit

Channeled array:
A set of transistors arranged with dedicated channels between rows of sets of tr
ansistors for interconnections.

CLB:
Complex Logic Block--the array of multi-input and multi-output logic cells to be
 programmed.

 NOTE: In Xilinx terminology, CLB is a configurable logic block. It consists mai
nly of LUTs
 and flip  flops. For more information on Xilinx devices, refer to 1996 Programm
able Logic
 Data Book from Xilinx.

CPLD:
Complex Programmable Logic Device

Embedded Array:
A hybrid of gate array and standard cell, where functional blocks like memory an
d µP are embedded into the base layers and the balance of the device is structur
ed as a sea-of-gates.

Full Custom:
A design style where all aspects--device size, interconnect, etc.--are available
 in the design palette.

Gate Array:
A collection of transistors that are configured by the user at the metal interco
nnect level(s) into logic functions. Architectures include gridded array, channe
led array, and sea of gates.

Gridded array:
A set of transistors arranged as a grid with spacing for interconnections on all
 four sides of the "core" cell.

LUT:
Look-Up Table--an alternative implementation of a CLB; the multiple inputs gener
ate the complex outputs.

Memory-based:
A type of programmable where the programming information for the interconnection
s is stored in memory. The memory is reprogrammable.

Non-volatile:
Type of memory or configuration that retains programmed information even when
no power is supplied to the device.  Examples of Non-volatile memory used for
logic switches are EPROM- or Flash-based CPLDs.

Pin locking:
Controling the assignment of a design's I/O signals to an established pin-out.

Pin pre-assigning:
Fixing or assigning a design's pin-out independent of the internal logic or esta
blished pin-out.

PLD:
Programmable Logic Device

Programmable FPGA:
Field Programmable Gate Array

RAM-based:
The driving memory for the interconnections is static RAM-based. It needs to be
powered up to retain programming information.

Routabilty:
The ability to make all of the connections desired.

Sea of Gates:
Channelless arrangement of transistors with routing space around each device, bu
t no defined routing areas.

Standard Cell:
A design style where the building blocks are placed into standard size areas, us
ually with a
fixed height and variable width for each cell. Intercell wiring is usually put i
nto channels.

Structured Custom:
A hybrid of standard cell and custom, where any design element can be changed, b
ut only from
a predefined selection of elements.

VIA or fuse (antifuse) :
One-time programmable, hard wiring changes by opening a link (fuse) or closing a
 link (antifuse).




End of Record #2736