Return to Support Page
 homesearchagentssupportask xilinxmap

Answers Database


Foundation XVHDL: Synthesis error "Wrong number of fields bus on line #__ in .xas file"


Record #2746

Product Family:  Software

Product Line:  Metamor

Problem Title:
Foundation XVHDL: Synthesis error "Wrong number of fields bus on line
#__ in .xas file"



Problem Description:
Keywords: Metamor, VHDL, Wrong, fields, bus, xas

Urgency: Standard

General Description:
Using Foundation XVHDL to synthesize the code, the following
error is reported:
"Wrong number of fields bus on line #__ in .xas file"


Solution 1:

A possible cause of this error is that in the VHDL code a
single bit was specified as a vector as shown below:

sig_name: out std_logic_vector(7 downto 7);

The solution is to change this to a single bit such as:

sig_name7: out std_logic;



End of Record #2746

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals!

© 1998 Xilinx, Inc. All rights reserved
Trademarks and Patents