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Considerations for choosing external PULLDOWN resistor values for FPGA pins.


Record #2765

Problem Title:
Considerations for choosing external PULLDOWN resistor values for FPGA
pins.



Problem Description:
Keywords: resistor, pulldown

Urgency: Standard

General Description:

When choosing a resistor value to be used as a pulldown for creating a Logic
LOW value on a pin during configuration there a three considerations to be
addressed:

1.  Quick solution, "Rule of Thumb" Rtyp (solution 1)
2.  What is the allowable voltage range? Rmax (solution 2)
3.  Will this pin be used as an output driver? Rmin (solution 3)


Solution 1:

1.  Quick solution, "Rule of Thumb" (solution 1)

For the quick solution or "Designing by Rule of Thumb" using a 3.3Kohm
pulldown should always work and never cause any problems.

For a fuller picture of how to find the acceptable range see solutions 2 & 3.



Solution 2:

2.  What is the allowable voltage range? (solution 1)

Use this solution to determine the maximum value for a pulldown resistor:

When the FPGA is in the unconfigured state, all I/Os have a week internal
pullup.  The internal pullup resistors range from 20Kohm to 50Kohm.  The
maximum allowable voltage level for the pin to be considered a `Logic Low'
depends on the Threshold standard used for the application (TTL or CMOS);
where, TTL-VOL=0.8Vmax and CMOS-VOL=1.0Vmax.  Since 0.8V will satisfy both
conditions we will use that for the example.

To calculate the maximum value for the external pulldown resistor (Rmax) we
will use the worstcase value for the internal pullup resistor (Rint) 20Kohms.

Where,

VOL = Vcc(Rmax/(Rmax + Rint)

Therefore,

Rmax = [(VOL*Rint/Vcc)/(1-(VOL/Vcc))]

Example,

Rmax = [((0.8)*(20000)/(5.0))/(1-(0.8)/(5.0))]
     = [(3200)/(0.84)]
     = [3.8kohms]



Solution 3:

3.  Will this pin be used as an output driver? (solution 2)

If the Pin is not to be used as an output driver then you may disregard this
solution.  Use this solution to determine the minimum value of the pulldown
resistor:

The VOH for an FPGA output driver has an associated current rating
corresponding to the threshold standard (TTL or CMOS).	Adding a pulldown
resistor to an active driver will increase the current sourced by that driver
during a Logic High output.  Therefore, the current through the pulldown
resistor (Rmin), in addition to any current sourced to additional resistive
loads, must not exceed the IOH rating.	If the total source current exceeds
the IOH rating, then the output voltage level may drop below the minimum
requirement for the specified threshold.

For example, for an xc4000E device, with outputs configured as TTL or CMOS,
the maximum source current rating is IOH=4mA or IOH=1mA, respectively.
However, for an xc4000XL device the maximum source current for TTL and CMOS
thresholds are 4mA and 500uA, repectively.  If the value of the pulldown
resistor (Rmin) is small enough to draw more than 500uA on the output of an
XL device, then the output logic high may not be sufficient enough to be
compatible with CMOS thresholds.

Therefore, to calculate Rmin we have:

Rmin = VOH/IOH ;

For example, continuing with a 5volt xc4000E TTL-threshold application, we
have:

Rmin = [(2.4V)/(4mA)]
     = [600 ohms]

If we were to run the calculation ofr a 3.3volt xc4000XL CMOS-threshold
application we would have:

Rmin = [(70%(Vcc))/IOH]
     = [(2.97V)/(1500uA)]
     = [2k ohms]

Note:  The VOH used is the standard for CMOS-VIH, and the IOH was calculated
by adding 500uA for each 10% drop from Vcc.



End of Record #2765