Answers Database

PAR/EPIC M1.5: Both say that BEL doesn't exist in the NCD, but it does.


Record #2777

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
PAR/EPIC M1.5: Both say that BEL doesn't exist in the NCD, but it does.


Problem Description:
Keywords: BEL, PAR, EPIC, timespec

Urgency: Standard

General Description:
PAR and EPIC both say that a BEL doesn't exist in the NCD, but it does. The
PCF file contains a TIMEGRP that contains the BEL.  When the NCD and PCF
files are loaded into either PAR or EPIC, they issue warnings that the BEL
was not found.	But visual inspection through EPIC confirms that the
BEL exist.


Solution 1:

The problem is this: when the mapper creates comps it will fill
them with the appropriate BELs.  With these bels you can attach
timing constraints.

The problem arises when you run the Logic Block Editor in EPIC
and modify a comp that contains bels.  Since a user cannot
guarantee that they'll always create a valid COMP, as far as
connectivity and programming, when they exit LBE then the COMP
will be turned into what is known as a 'SuperBel' where the system
treats the entire COMP as a BEL.  Hence any BELs internal to that
comp will be obliterated thus rendering any timing constraints,
which reference those BELs, useless.

This is a known problem.  The only workaround is not to modify
CLB's, IOB's, or other COMPs that are pointed to by a time group
or a timing constraint.



End of Record #2777