Answers Database

XC9500: Logic erroneously trimmed away when using HDL macros in 9k schematic design


Record #2780

Product Family:  Software

Product Line:  EPLD Core

Problem Title:
XC9500:	Logic erroneously trimmed away when using HDL macros in 9k
schematic design



Problem Description:
Keywords:  9500, CPLD, trim, VHDL

Urgency:  Standard

General Description:

This problem occurs when an HDL macro drives 2 or more of its
output pins from the same net. The problem has been confirmed
with Metamor and Exemplar netlists; Synopsys DC netlists avoid
this problem. Symptom is that all logic in the schematic
sourced by all but one of the duplicate macro pins is trimmed
from the design. That is, only one of the commonly-sourced
macro pins will remain connected; which one is arbitrary.

For example, the following problematic HDL macro produces 2
outputs driven by the same net (only one flop is inferred):

entity afd is
    port (din: in STD_LOGIC;
	clk : in STD_LOGIC;
	dout1, dout2 : out STD_LOGIC);
end afd;
architecture afd_arch of afd is
begin
process (CLK)
begin
   if CLK'event and CLK='1' then
      DOUT1 <= DIN;
      DOUT2 <= DIN;
   end if;
end process;
end afd_arch;



Solution 1:

This problem was reported in CR 100105 and will be fixes in the
1.4 release.

For M1.3, a possible workaround for Foundation XVHDL (Metamor)
is to create an internal intermediate signal for each
commonly-driven output port, and assign the Metamor "critical"
attribute to each signal, as follows:

library METAMOR;
use METAMOR.attributes.all;
entity afd is
    port (din: in STD_LOGIC;
	clk : in STD_LOGIC;
	dout1, dout2 : out STD_LOGIC);
end afd;
architecture afd_arch of afd is
signal q1, q2 : STD_LOGIC;
    attribute critical of q1 : signal is true;
    attribute critical of q2 : signal is true;
begin
process (CLK)
begin
   if CLK'event and CLK='1' then
      q1 <= DIN;
      q2 <= DIN;
   end if;
end process;
DOUT1<=q1;
DOUT2<=q2;
end afd_arch;



End of Record #2780