Return to Support Page
 homesearchagentssupportask xilinxmap

Answers Database


M1.3.7, M1.4.12 LOGIBLOX: rloc_orgin on Logiblox ADD/SUBis ignored by place and route tool.


Record #2782

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
M1.3.7, M1.4.12 LOGIBLOX: rloc_orgin on Logiblox ADD/SUBis ignored by
place and route tool.



Problem Description:
KEYWORDS: Logiblox, rloc_orgin, rloc, ignored, RPM, adder, subtractor, par

URGENCY: Standard

GENERAL DESCRIPTION
The rloc_orgin attribute assigned to adders or subtractors created by Logiblox m
ay appear to be ignored by the place and
route tool.

The reason for this is logiblox does not assign RPMs (RLOCs) to adders and subtr
actors.  There are RLOCs which are used to define what goes inside individual CL
Bs, but there are no RLOCs provided for each CLBs.  And since there are no RLOCs
 for CLBs, there are no h_set for the whole adder/subtractor.  And RLOC_ORGIN as
signment will only work with RLOCs.  Therefore, assigning RLOC_ORGIN to adder or
 subtractor will not work.  The M1 tool will just ignore this RLOC_ORGIN and wil
l NOT give you any warning or error messages.

You can verify that this is the case by opening the place and routed design in t
he EPIC editor, and see where the add and/or subtractors are place.

Reference #: 102618


Solution 1:

Workaround for this problem is to manually assign the RLOCs for the indivicual C
LBs of the adder and subtractor.

You can do this by finding out what the CLB names are for all the components of
the adder/subtractor and assign rloc statement in the .pcf file.



End of Record #2782

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals!

© 1998 Xilinx, Inc. All rights reserved
Trademarks and Patents