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Model Tech: Error can not read output when compiling backannotated 9500 VHDL


Record #2792

Problem Title:
Model Tech: Error can not read output when compiling backannotated 9500
VHDL



Problem Description:
Keywords:  CPLD, 9500, model tech, MTI

Urgency:  Standard

General Description:
In a 9500 design if you are using pin feedback you will get the following error
when you compile the backannotated VHDL file in model tech V-system:

######TIME_SIM.VHD(2919): port map(I => FLASH_CE(0), O => FLASH_CE_O_PIN_BUF_0);


######TIME_SIM.VHD(2919): Cannot read output flash_ce.

With pin feedback an INTERNAL signal is fed through the buffers in the I/O block
 back into the 9500. The problem is what V-System sees is a signal is declared a
 signal but later is used as an I/O as it passes through the I/O buffer. It is i
llegal to have a signal used as an I/O in VHDL.


Solution 1:

The only work around at present is to NOT use pin feedback if you want to timing
 simulate your design using Model Tech V-System.

To not use pin feedback, de-select the check box in the GUI
'Use Pin Feedback'.  This option can be found by going to
Implement -> Options -> Edit Template -> Optimization Tab ->
Use Local I/O Pin Feedback.  Also if using the CPLD command, do not use the '-pi
nfbk' option.

Alternatively use pin feedback and not simulate, functionally simulate and use t
he timing analyzer to ensure the design runs to speed.



End of Record #2792