Answers Database

SYNPLIFY: How to instantiate BSCAN in HDL (Verilog/VHDL)?


Record #2805

Problem Title:
SYNPLIFY: How to instantiate BSCAN in HDL (Verilog/VHDL)?


Problem Description:
Keywords: bscan, Verilog, VHDL, synplicity, xc4000, xc5200

Urgency: Standard

General Description: How to instantiate BSCAN in HDL for
Synplicity?

The BSCAN component indicates that boundary scan logic should
be enabled after the programmable logic device (PLD) configuration
is complete.  It also provides optional access to some special
features of the XC5200 boundary scan logic.  To indicate that BSCAN
remains enabled after configuration, connect the BSCAN component
to the TDI, TMS, TCK, and TDO pins.


Solution 1:

// XC5200 - Boundary SCAN Verilog code

module bnd_scan (a, b, c);

input  a, b;
output c;
reg c;

wire TCK_P, TDI_P, TMS_P, TDO_P;

BSCAN U0 (.TDO (TDO_P), .TDI (TDI_P), .TMS (TMS_P), .TCK (TCK_P));

TDI U1 (.i (TDI_P));

TCK U2 (.i (TCK_P));

TMS U3 (.i (TMS_P));

TDO U4 (.o (TDO_P));

always@ (posedge b)
	c<=a;

endmodule

module TDI(i) /* synthesis black_box */;
output i /* synthesis .ispad=1 */;
endmodule

module TCK(i) /*synthesis black_box*/;
output i /*synthesis .ispad=1*/;
endmodule

module TMS(i) /*synthesis black_box*/;
output i /*synthesis .ispad=1*/;
endmodule

module TDO(o) /*synthesis black_box .noprune=1 */;
input  o /*synthesis .ispad=1*/;
endmodule

module BSCAN(TDO, TCK, TDI, TMS) /* synthesis black_box */;
  output TDO;
  input TCK, TDI, TMS;
endmodule


#-- TCL Script

#device options
set_option -technology XC5200
set_option -part XC5202
set_option -package PC84
set_option -speed_grade -3

#add_file options
add_file -verilog "bnd_scan.v"

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler true

#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -force_gsr true
set_option -disable_io_insertion false
set_option -xilinx_m1 true

#set result format/file last
project -result_file "bnd_scan.xnf"
project -run

#end TCL



Solution 2:

You can instantiate a BSCAN cell by using the import library supplied
with Synplify. The Synplify Xilinx Macro Libraries contain pre-defined
black-boxes for the Xilinx macros so that you can manually instantiate
them into your design.

For VHDL based designs all one has to do is add the following 2 lines
in the VHDL and instantiate the BSCAN component. Please look in the
$SYNPLCTY\lib\xilinx\xc4000.vhd for BSCAN component and its port
interface list.  For xc5200 VHDL designs, use xc4000.vhd "black box"
instantiation as an example.
	
	library xc4000;
	use xc4000.components.all;

For Verilog designs, just add the xc4000.v file in the source file list
along with the source design file. The xc4000.v file is also in the
$SYNPLCTY\lib\xilinx directory. For xc5200 Verilog designs, use xc4000.v
black box instantiation as an example.

Note: You must instantiate the complete set of Xilinx boundary scan modules
(bscan,tdi,tck,tms,tdo) in to your design.



Solution 3:

// XC4000e/ex/xl - Boundary SCAN Verilog code

module bnd_scan (a, b, c);

input  a, b;
output c;
reg c;

wire TCK_P, TDI_P, TMS_P, TDO_P;

BSCAN U1 (.TDO (TDO_P), .TDI (TDI_P), .TMS (TMS_P), .TCK (TCK_P),
	  .DRCK (open), .IDLE (open), .SEL1 (open), .SEL2 (open),
		.TDO1 (1'b0), .TDO2 (1'b0));

TDI U2 (.i (TDI_P));

TCK U3 (.i (TCK_P));

TMS U4 (.i (TMS_P));

TDO U5 (.o (TDO_P));

always@ (posedge b)
	c<=a;

endmodule


#-- TCL scipt

#device options
set_option -technology XC4000E
set_option -part XC4003E
set_option -package PC84
set_option -speed_grade -1

#add_file options
add_file -verilog "/products/synplify.ver3_0/lib/xilinx/xc4000.v"
add_file -verilog "bnd_scan.v"

#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -force_gsr true
set_option -disable_io_insertion false
set_option -xilinx_m1 true

#set result format/file last
project -result_file "bnd_scan.xnf"
project -run

#end TCL



Solution 4:

-- XC4000e/ex/xl - Boundary SCAN VHDL code

library IEEE;
use IEEE.std_logic_1164.all;
library xc4000;
use xc4000.components.all;

entity bnd_scan is
    port (
	  a, b: in bit;
	  c: out bit
	);
end bnd_scan;

architecture xilinx of bnd_scan is

signal TCK_P : STD_LOGIC;
signal TDI_P : STD_LOGIC;
signal TMS_P : STD_LOGIC;
signal TDO_P : STD_LOGIC;

begin

    U0: BSCAN port map (TDO  => TDO_P,
			TDI  => TDI_P,
			TMS  => TMS_P,
			TCK  => TCK_P,
			DRCK => open,
			IDLE => open,
			SEL1 => open,
			SEL2 => open,
			TDO1 => '0',
			TDO2 => '0');

    U1: TDI port map (I =>TDI_P);

    U2: TCK port map (I =>TCK_P);

    U3: TMS port map (I =>TMS_P);

    U4: TDO port map (O =>TDO_P);

process (b)
begin if (b'event and b='1')
	then c <= a;
end if;
end process;

end xilinx;


#-- TCL script

#device options
set_option -technology XC4000E
set_option -part XC4003E
set_option -package PC84
set_option -speed_grade -1

#add_file options
add_file -vhdl -lib work "bnd_scan.vhd"
add_file -_include "/products/synplify.ver3_0/lib/xilinx/xc4000.vhd"

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler false

#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -force_gsr true
set_option -disable_io_insertion false
set_option -xilinx_m1 true

#set result format/file last
project -result_file "bnd_scan.xnf"
project -run

#end TCL


Note: If you experience problems instatiating,
the simplest workaround for you would be to replace the
VHDL "open" statements with actual signal names.
All you have to do is declare 4 signals of type std_logic
and connect the DRCK, IDLE, SEL1 and SEL2 ports of BSCAN
to these signals.

Another solution that would work requires a change in the
BSCAN component declaration in the xc4000.vhd file
located in your SYNPLCTY\LIB\xilinx directory.

Please change the BSCAN component to be

component BSCAN

   port(
      TDO			     :	out   STD_LOGIC ;
      DRCK			     :	out   STD_LOGIC ;
      IDLE			     :	out   STD_LOGIC ;
      SEL1			     :	out   STD_LOGIC ;
      SEL2			     :	out   STD_LOGIC ;
      TDI			     :	in    STD_LOGIC;
      TMS			     :	in    STD_LOGIC;
      TCK			     :	in    STD_LOGIC;
      TDO1			     :	in    STD_LOGIC;
      TDO2			     :	in    STD_LOGIC);
end component;


Notice that the initialization for the output ports have been
removed.



Solution 5:

-- XC5200 - Boundary Scan VHDL code

library IEEE;
use IEEE.std_logic_1164.all;

entity bnd_scan is
    port (a, b : in bit;
	  c : out bit);
end bnd_scan;

architecture xilinx of bnd_scan is
    attribute black_box : boolean;
    attribute black_box_pad_pin : string;
    attribute synthesis_noprune : boolean;

    component BSCAN
	port (TDI, TMS, TCK : in STD_LOGIC;
	      TDO : out STD_LOGIC);
    end component;
    attribute black_box of BSCAN : component is true;

    component TDI
	port (I : out STD_LOGIC);
    end component;
    attribute black_box_pad_pin of TDI : component is "I";

    component TCK
	port (I : out STD_LOGIC);
    end component;
    attribute black_box_pad_pin of TCK : component is "I";

    component TMS
	port (I : out STD_LOGIC);
    end component;
    attribute black_box_pad_pin of TMS : component is "I";

    component TDO
	port (O : in STD_LOGIC);
    end component;
    attribute black_box_pad_pin of TDO : component is "O";
    attribute synthesis_noprune of TDO : component is true;

signal TCK_P : STD_LOGIC;
signal TDI_P : STD_LOGIC;
signal TMS_P : STD_LOGIC;
signal TDO_P : STD_LOGIC;

begin

    U0: BSCAN port map (TDO  => TDO_P,
			TDI  => TDI_P,
			TMS  => TMS_P,
			TCK  => TCK_P);

    U1: TDI port map (I =>TDI_P);

    U2: TCK port map (I =>TCK_P);

    U3: TMS port map (I =>TMS_P);

    U4: TDO port map (O =>TDO_P);

process (b)
begin
if (b'event and b='1') then
	c <= a;
end if;
end process;

end xilinx;


#-- TCL Script

#device options
set_option -technology XC5200
set_option -part XC5202
set_option -package PC84
set_option -speed_grade -3

#add_file options
add_file -vhdl -lib work "bnd_scan.vhd"

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler false

#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -force_gsr true
set_option -disable_io_insertion false
set_option -xilinx_m1 true

#set result format/file last
project -result_file "bnd_scan.xnf"
project -run

#end TCL



End of Record #2805