Answers Database

SYNPLIFY: How to force a IOB NODELAY latch or flip-flop in HDL (Verilog/VHDL)?


Record #2831

Problem Title:
SYNPLIFY: How to force a IOB NODELAY latch or flip-flop in HDL
(Verilog/VHDL)?



Problem Description:
Keywords: synplify, Verilog, VHDL, 5200, 4000, nodelay

Urgency: Standard

General Description:

XC4000e/ex/xl IOB flip-flops and latches have a delay block between the
external pin and the D input.  The xc5200 IOB, also, provides a programmable
delay element to control input set-up time.  This delay prevents any possible
hold-time violations if you have a clock signal that is also coming into the
device and clocking the input flip-flop or latch.  You can remove this delay
with the NODELAY attribute. The NODELAY attribute decreases the setup-time
requirements and introduces a small hold-time.


Solution 1:

-- XC4000e/ex/xl and xc5200 -- VHDL code
-- Passing NODELAY through a constraints file (.sdc)

library IEEE;
use IEEE.std_logic_1164.all;

entity ifd_ex is
    port (CLK, A, B: in STD_LOGIC;
	  O: out STD_LOGIC);
end ifd_ex;

architecture xilinx of ifd_ex is

signal Q : STD_LOGIC;

begin
U0: process (CLK)
    begin
	if (CLK'event and CLK='1') then
	    Q <= A;
	end if;
    end process;

-- token logic
O <= Q and B;

end xilinx;


# Vendor specific constraints are passed in an .sdc file
define_attribute A xc_nodelay 1


#-- TCL script
#-- Passing NODELAY through a constraints file

#device options
#for this example, you can change the device to 5200
set_option -technology XC4000E
set_option -part XC4003E
set_option -package PC84
set_option -speed_grade -1

#add_file options
add_file -constraint "ifd_ex.sdc"
add_file -vhdl -lib work "ifd_ex.vhd"

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler false

#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -force_gsr true
set_option -disable_io_insertion false
set_option -xilinx_m1 true

#set result format/file last
project -result_file "ifd_ex.xnf"
project -run

#end TCL



Solution 2:

For xc4000e/ex/xl, you can remove the default delay by instantiating a
flip-flop or latch with a NODELAY attribute. Input flip-flops or latches
with an _F suffix have a NODELAY attribute assigned to the cell. For example,
the components IFD_F or ILD_1F remove this delay because these cells include a
NODELAY attribute.

However, since the xc5200 IOB does not include flip-flops or latches. The
xc5200 family provides direct connections from each IOB to the registers in the
adjacent CLB in order to emulate IOB registers.

The designer has the option of passing the "xc_nodelay" attribute through a
constraints file (.sdc) or the HDL code.



Solution 3:

// XC4000e/ex/xl only -- Verilog code
// Instantiate an IFD_F

module ifd_ex (CLK, A, B, O);

input A ;
input B, CLK;
output O;

wire Q;

IFD_F U0 (.Q (Q), .D (A), .C (CLK));

// token logic
assign O = Q & B;

endmodule


#-- TCL scipt
#-- Instantiating IFD_F

#device options
set_option -technology XC4000E
set_option -part XC4003E
set_option -package PC84
set_option -speed_grade -1

#add_file options
add_file -verilog "/products/synplify.ver3_0/lib/xilinx/xc4000.v"
add_file -verilog "ifd_ex.v"

#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -force_gsr true
set_option -disable_io_insertion false
set_option -xilinx_m1 true

#set result format/file last
project -result_file "ifd_ex.xnf"
project -run

#end TCL



Solution 4:

// XC4000e/ex/xl and xc5200 -- Verilog code
// Passing NODELAY through HDL

module ifd_ex (CLK, A, B, O);

input A /* synthesis xc_nodelay=1 */;
input B, CLK;
output O;

reg Q;

    always @ (posedge CLK)
    begin
	  Q <= A;
    end

// token logic
assign O = Q & B;

endmodule


#-- TCL scipt
#-- Passing NODELAY through HDL

#device options
#for this example, you can change the device to 5200
set_option -technology XC4000E
set_option -part XC4003E
set_option -package PC84
set_option -speed_grade -1

#add_file options
add_file -verilog "ifd_ex.v"

#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -force_gsr true
set_option -disable_io_insertion false
set_option -xilinx_m1 true

#set result format/file last
project -result_file "ifd_ex.xnf"
project -run

#end TCL



Solution 5:

// XC4000e/ex/xl and xc5200 -- Verilog code
// Passing NODELAY through a contraints file (.sdc)

module ifd_ex (CLK, A, B, O);

input A;
input B, CLK;
output O;

reg Q;

    always @ (posedge CLK)
    begin
	  Q <= A;
    end

// token logic
assign O = Q & B;

endmodule


# Vendor specific constraints are passed in an .sdc file
define_attribute A xc_nodelay 1


#-- TCL scipt
#-- Passing NODELAY through a constraints file

#device options
#for this example, you can change the device to 5200
set_option -technology XC4000E
set_option -part XC4003E
set_option -package PC84
set_option -speed_grade -1

#add_file options
add_file -constraint "ifd_ex.sdc"
add_file -verilog "ifd_ex.v"

#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -force_gsr true
set_option -disable_io_insertion false
set_option -xilinx_m1 true

#set result format/file last
project -result_file "ifd_ex.xnf"
project -run

#end TCL



Solution 6:

-- XC4000e/ex/xl only -- VHDL code
-- Instantiate an IFD_F

library IEEE;
use IEEE.std_logic_1164.all;
library xc4000;
use xc4000.components.all;

entity ifd_ex is
    port (CLK, A, B : in STD_LOGIC;
	  O : out STD_LOGIC);
end ifd_ex;

architecture xilinx of ifd_ex is

signal Q : STD_LOGIC;

begin
U0 : IFD_F port map (Q => Q,
		     D => A,
		     C => CLK);
-- token logic
O <= Q and B;

end xilinx;


#-- TCL script
#-- Instaniating IFD_F

#device options
set_option -technology XC4000E
set_option -part XC4003E
set_option -package PC84
set_option -speed_grade -1

#add_file options
add_file -vhdl -lib work "ifd_ex.vhd"

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler false

#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -force_gsr true
set_option -disable_io_insertion false
set_option -xilinx_m1 true

#set result format/file last
project -result_file "ifd_ex.xnf"
project -run

#end TCL



Solution 7:

-- XC4000e/ex/xl and xc5200 -- VHDL code
-- Passing NODELAY through HDL

library IEEE;
use IEEE.std_logic_1164.all;

entity ifd_ex is
    port (CLK, A, B: in STD_LOGIC;
	  O: out STD_LOGIC);

attribute xc_nodelay : boolean;
attribute xc_nodelay of A : signal is true;

end ifd_ex;

architecture xilinx of ifd_ex is

signal Q : STD_LOGIC;

begin
U0: process (CLK)
    begin
	if (CLK'event and CLK='1') then
	    Q <= A;
	end if;
    end process;

-- token logic
O <= Q and B;

end xilinx;

#-- TCL script
#-- Passing NODELAY through HDL

#device options
#for this example, you can change the device to 5200
set_option -technology XC4000E
set_option -part XC4003E
set_option -package PC84
set_option -speed_grade -1

#add_file options
add_file -vhdl -lib work "ifd_ex.vhd"

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler false

#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -force_gsr true
set_option -disable_io_insertion false
set_option -xilinx_m1 true

#set result format/file last
project -result_file "ifd_ex.xnf"
project -run

#end TCL



End of Record #2831