Answers Database

FPGA/Design Compiler: How to instantiate LogiBLOX in the Synopsys VHDL or Verilog Flow


Record #2865

Product Family:  Software

Product Line:  Synopsys

Problem Title:
FPGA/Design Compiler: How to instantiate LogiBLOX in the Synopsys VHDL
or Verilog Flow



Problem Description:
keywords: FPGA, Design, Compiler,FPGA Compiler, Design Compiler,LogiBLOX, RAM. i
nstantiate, VHDL, Verilog

urgency: standard

general description:

How to instantiate LogiBLOX .ngo files in a VHDL or Verilog design,
using FPGA Compiler.  The runscripts for the VHDL and Verilog examples
are for FPGA Compiler.	The same scripts can be used for Design Compiler
if the 'replace_fpga' command is removed.


Solution 1:

How to instantiate LogiBLOX in a FPGA Compiler VHDL design

Note: This example uses a LogiBLOX synchronous RAM.  The procedure
used can be applied to instantiating any LogiBLOX.

(1) For an eample VHDL code using LogiBLOX RAM, and VHDL runscript,
open the Dynatext book 'Synopsys (XSI) Interface/Tutorial Guide'. Next,
in the 'Search:' box type and then hit the 'search' button:

Instantiating RAM using LogiBLOX VHDL Example

(2) Create a LogiBLOX memory.  A .ngo and .vhi file are created.

(3) Use the .ngo file name as the name of the 'component' instantiation
in the VHDL code. The .vhi file will contain the pin names and port map
needed to instantiate the LogiBLOX memory.

(4) Place a 'dont_touch' on the instantiated LogiBLOX.	If you have multiple
instantiations of LogiBLOX, place a 'dont_touch' on each of the instantiations.

(5) Synthesize the design. Note the example runscript is no different from
the normal M1 FPGA Compiler runscript.




Solution 2:

VHDL Code Example:

library IEEE;use IEEE.std_logic_1164.all;
entity test is
port (ADDRESS: IN std_logic_vector(5 downto 0);
	DATAOUT: OUT std_logic_vector(3 downto 0);
	DATAIN: IN std_logic_vector(3 downto 0);
	WRITEN: IN std_logic;
	CLK: IN std_logic);
end test;
architecture inside of test is
component testram
	port (A: IN std_logic_vector(5 downto 0);
	     DO: OUT std_logic_vector(3 downto 0);
	     DI: IN std_logic_vector(3 downto 0);
	     WR_EN: IN std_logic;
	     WR_CLK: IN std_logic);
end component;
begin
U0: testram port map(A=>ADDRESS,DO=>DATAOUT,DI=>DATAIN,
    WR_EN=>WRITEN,WR_CLK=>CLK);
end inside;





Solution 3:

VHDL Runscript Example for a LogiBLOX Design:

analyze -f vhdl "test.vhd"
elaborate test

set_port_is_pad "*"
insert_pads


compile

replace_fpga

ungroup -all -flatten


write_script > test.dc

sh dc2ncf test.dc

write -f xnf -h -o "test.sxnf"



Solution 4:

How to instantiate LogiBLOX in a Synopsys Verilog Design


Note: This example uses a LogiBLOX synchronous RAM.  The procedure
used can be applied to instantiating any LogiBLOX.

(1) For an eample VHDL code using LogiBLOX RAM, and VHDL runscript,
open the Dynatext book 'Synopsys (XSI) Interface/Tutorial Guide'. Next,
in the 'Search:' box type and then hit the 'search' button:

Instantiating RAM using LogiBLOX Verilog Example

(2) Create a LogiBLOX memory.  A .ngo and .vei file are created.

(3) Use the .ngo file name as the name of the 'module' instantiation
in the Verilog code. The .vei file will contain the pin names and port map
needed to instantiate the LogiBLOX memory.

(4) In the .vei file, there is a 'module' description of the LogiBLOX.
The module description describes the pin names and pin directions.  Place
these lines in a seperate file and read them into the Synopsys during
the compile of the design.  Create an empty Verilog file, which only
contains the LogiBLOX module name, pin names, and pin directions, for
each type of LogiBLOX instantiated in the Verilog code.

(5) Place a 'dont_touch' on the instantiated LogiBLOX.	If you have multiple
instantiations of LogiBLOX, place a 'dont_touch' on each of the instantiations.

(6) Synthesize the design. Note the example runscript is no different from
the normal M1 FPGA Compiler runscript.

(7) Note, just before writing out the .sxnf or .sedif file, the LogiBLOX
design is removed using the 'remove_design' command.  This prevents
Synopsys from writing out an empty file for the LogiBLOX design; If you
are using LogiBLOX, you already have a .ngo file that represents the
LogiBLOX.  If Synopsys writes out an empty file for the LogiBLOX
module , large portions of yourdesign could get deleted.
A 'remove_design' must be done for every empty Verilog file created from
step (4) above.







Solution 5:

Verilog Code Example:

File1:

module test(address,dataout,datain,writen,clk);input [5:0] address;
output [3:0] dataout;
input [3:0] datain;
input writen;
input clk;
testram U0
( .A(address),
  .DO(dataout),
  .DI(datain),
  .WR_EN(writen),
  .WR_CLK(clk));
endmodule



File2:

module testram(A, DO, DI, WR_EN, WR_CLK);input [5:0] A;
output [3:0] DO;
input [3:0] DI;
input WR_EN;
input WR_CLK;
endmodule



Solution 6:

Verilog Runscript Example for a LogiBLOX Design:


read -f verilog "testram.v"
read -f verilog "test.v"

set_port_is_pad "*"
insert_pads

compile

replace_fpga

ungroup -all -flatten

write_script > test.dc

sh dc2ncf test.dc

remove_design testram

write -f xnf -h -o "test.sxnf"



End of Record #2865