Answers Database

FPGA Express 1.2, 2.0: XC4000 Global Buffer constraints: ERROR:baste:263


Record #2888

Product Family:  Software

Product Line:  Synopsys

Problem Title:
FPGA Express 1.2, 2.0: XC4000 Global Buffer constraints: ERROR:baste:263


Problem Description:
Keywords: Map, BUFGP, BUFGS, XL, EX, FPGA EXPRESS, 1.2, 2.0, LOC, pin
constraints, clock

Urgency: Standard

General Description:

In MAP the following error is reported:

ERROR:baste:263 - The LOC constraint "BUFG_WNW, BUFGE_WNW, BUFGLS_WNW"
(a BUFG location) is not valid for BUFGS symbol "<symbol name>"
(output signal=<signal name>), which is being mapped to the following site
types:	      BUFGLS

Cause:
FPGA Express puts location constraints onto the global buffer instead of on
the pad (EXT record).  If you attempt to place a standard "Pxx" pin location
constraint on a clock within Express, this error will occur.


This problem has been resolved with Express patch version 2.0.3.  Please see
(Xilinx Solution 3566) to download this patch.


Solution 1:

Instead of using the pin number to constrain the clock, use the clock buffer
name and location.  Each XC4000EX/XL clock buffer is designated by a position
name.

GCK1 = BUFGLS_WNW
GCK2 = BUFGLS_WSW
GCK3 = BUFGLS_SSW
GCK4 = BUFGLS_SSE
GCK5 = BUFGLS_ESE
GCK6 = BUFGLS_ENE
GCK7 = BUFGLS_NNE
GCK8 = BUFGLS_NNW

Each GCKs corresponding pin number can be found in the pinout table for the
particular package used.

For XC4000E, the syntax is slightly different:

BUFGP_TL, BUFGP_TR, BUFGP_BL, BUFGP_BR,
BUFGS_TL, BUFGS_TR, BUFGS_BL, BUFGS_BR,

In FPGA Express:
1. Create an implementation.
2. Double click on the current Implemenation and select the Ports tab.
3. Under Pad Loc, replace the pin number with the GCK location name.



Solution 2:

Another option is to place the pin location constraint in the UCF file using
the following syntax:

NET <clock_port_name> LOC = P<pin_number>;



End of Record #2888