Answers Database

Foundation F1.3/F1.4 Schematic: How to lock down I/O pins for IPAD4/8/16, OPAD4/8/16, IOPAD/4/8/16


Record #2895

Product Family:  Software

Product Line:  Aldec

Problem Title:
Foundation F1.3/F1.4 Schematic: How to lock down I/O pins for
IPAD4/8/16, OPAD4/8/16, IOPAD/4/8/16



Problem Description:
Keywords: foundation, F1.3, F1.4, Schematics, Lock, Loc,
	  logiblox

Urgency: Standard

General Description:

How to lock down pins for IPAD4/8/16, OPAD4/8/16, IOPAD/4/8/16


Solution 1:

One way is by using the Logiblox utility.
**Note:  Logiblox is only available with FPGA designs.
For CPLDs, see Resolutions 2 and/or 3.

1. In the Foundation Project Manager, select Tools ->
   Logiblox
2. Select Module Type -> Pads (either input, output, or
   bi-directional)
3. The Pad Loc attribute specifies the pin location for
   an I/O pad.

Usage: To assign a location to a specific bit, precede the location
with a bit identifier. You can assign multiple bits
by using a period as a separator. For example, with a bus
width of 8 bits, you could have the following assignment:

PAD_LOC=0:P44.2:P45.7:P46

This specification assigns bit 0 to pad 44, bit 2 to pad 45,
and bit 7 to pad 46

Note: Commas will not work as separators between bit assignments.





Solution 2:

Another method is by using a UCF (User Constraints File).

For instance a bus named A[7:0] (between the IPAD8/OPAD8
and IBUF8/OBUF8) can be pin-locked by using the following
syntax in the UCF:

NET A<7> LOC = P18;
NET A<6> LOC = P19;
NET A<5> LOC = P20;
NET A<4> LOC = P23;
NET A<3> LOC = P24;
NET A<2> LOC = P25;
NET A<1> LOC = P26;
NET A<0> LOC = P27;

If the PAD is in a lower level of hierarchy (ie, anything but
the top-level), then use the following syntax:

NET INSTANCE_NAME/A0 LOC = P15;

where INSTANCE_NAME is the name of the hierarchical block, and
A0 is the 0 bit of the A bus.  Notice that you should NOT use
the <> brackets around the bit number of the bus.



Solution 3:

If you are designing for a 9500 CPLD, you may also use the
.GYD file to lock your pins.  The .GYD file is created
automatically when the design is fit.  It contains the pinout
of the fitted design.  The .GYD file may also be editted with
a text editor to modify or change the pin assignments.	After
the .GYD file has been modified, ensure that when you are
Implementing the design, the appropriated GYD file is
selected in the Implementation Options dialog box.  This will
ensure that the pinout in the GYD file is used.



End of Record #2895