Answers Database

M1.4: NGD2VER writes out the GR pin as a port in XC3000A netlists


Record #2931

Product Family:  Software

Product Line:  Merged Core

Problem Title:
M1.4:  NGD2VER writes out the GR pin as a port in XC3000A netlists


Problem Description:
Keywords: GR, functional simulation, 3k, 3000A, verilog
NGD2VER, HDL Direct, concept2xil

Urgency: standard

General Description:
XC3000A Verilog netlists generated by NGD2VER specify the 3K
global reset signal as a Verilog port called "GR" at all
points of the flow.  This is inconsistent with the XC3000
Concept Unified library, in which the GR signal is
implemented as a hidden signal, and in the Verilog Unified
Library model for flipflops, in which GR is a wire
defined by a GR_SIGNAL macro (See the Xilinx Cadence
Interface/Tutorial guide for more information).

The repercussion of this inconsistency is that it causes a
mismatch with the way GR is represented in pre-NGDBUILD
Concept HDL Direct functional simulation and post-NGDBUILD
simulation using NGD2VER that prevents you from using the
same test bench in both simulations.

In HDL Direct functional simulation flow, CONCEPT2XIL is
executed with a -sim_only option to generate a functional
simulation netlist directly from the Concept Unified Library
schematics.  This netlist models GR as an embedded Verilog
wire.

Reference #: 100137


Solution 1:

Use separate test fixtures for Concept HDL Direct functional
simulations and NGD2VER simulations.



End of Record #2931