Answers Database

Foundation F1.3/F1.4 XVHDL : I/O flip-flops (IFDX1) instantiation


Record #2954

Product Family:  Software

Product Line:  Aldec

Problem Title:
Foundation F1.3/F1.4 XVHDL : I/O flip-flops (IFDX1) instantiation


Problem Description:
Keywords: flops, ff, ifd, ifdx

Urgency : Standard

General description:
In XVHDL, beside inferring I/O flip-flops using map option
(Xilinx Solution 2772) you can also instantiate them individually.


Solution 1:

The following is an example of instantiating an input
flip-flop, in this case, an IFDX1.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY METAMOR;
USE METAMOR.attributes.all;

ENTITY TEST IS
 PORT(clock		       : IN STD_LOGIC;
       mux_in			: IN STD_LOGIC;
       mux_out			: OUT STD_LOGIC);
  attribute inhibit_buf : boolean;
  attribute inhibit_buf of clock, mux_in: signal is true;
END TEST;

architecture INSIDE OF TEST IS

  COMPONENT bufg
  PORT(i		: IN STD_LOGIC;
       o		: OUT STD_LOGIC);
  END COMPONENT;

  PORT(ce		: IN STD_LOGIC;
       c		: IN STD_LOGIC;
       d		: IN STD_LOGIC;
       q		: OUT STD_LOGIC);
  END COMPONENT;

  SIGNAL clock_s		: STD_LOGIC;

BEGIN
  u0 : bufg PORT MAP (i => clock, o => clock_s);
  u1 : ifdx1 PORT MAP ( ce => '0', c => clock_s, d => mux_in,
			q => mux_out);

end INSIDE;



End of Record #2954