Return to Support Page
 homesearchagentssupportask xilinxmap

Answers Database


M1.5 TRCE: How to find the signals not covered by TIMESPECs?


Record #2963

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
M1.5 TRCE: How to find the signals not covered by TIMESPECs?


Problem Description:
keywords: trce

Urgency: Standard

General Description: In the constraints covered section of the .twr file, 99.1%
(for, example) is covered.  How do you find the the 0.9% of connections not cove
red?


Solution 1:

The percentage of connections covered by timing constraints
is given in a "% coverage" statistic. The statistic does not
indicate the percentage of paths covered; it indicates the
percentage of connections covered. Even if you have entered
constraints that cover all paths in the design, this
percentage may be less than 100%, since some connections are
never included for timing analysis (for example, connections
to the STARTUP component).

If the user timespecs are incomplete, then he/she may do a
Path Filters->Timing Constraint Filters->Report Paths Not
Covered By Timing constraints.

This will add a default group to the timing report that
covers the unconstrained paths in the design (except for the
connections that are never included, mentioned above).



Solution 2:

One other thing to be aware with missing connections is the use of TIG (timing i
gnore) or use of any of the Path Tracing Controls (i.e. tbuf_i_o disable).  Thes
e also remove connections from the 100% statistic.



End of Record #2963

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals!

© 1998 Xilinx, Inc. All rights reserved
Trademarks and Patents