Return to Support Page
 homesearchagentssupportask xilinxmap

Answers Database


M1.3: How to include -ul option in NGD2VER within Design Manager


Record #2977

Product Family:  Software

Product Line:  Merged Core

Problem Title:
M1.3: How to include -ul option in NGD2VER within Design Manager


Problem Description:
Keywords: -ul, ngd2ver, Verilog-XL, Verilog, dsgnmgr, Design Manager

Urgency: Standard

General Description:

In order to simulate Verilog simulation files with Verilog-XL,
user needs to run NGD2VER with '-ul' option.  User needs to add
this with Template Manager in Design Manager.


Solution 1:

Start 'dsgnmgr'
Select 'Utilities->Template Manager'
Click on 'Customize..'

Program Name: ngd2ver
Program Options: -ul
Click on 'Set'
make sure the option shows up in the template
Click on 'OK'
Close 'Template Manager'

Select 'Design->Implement'
Click on 'Edit Template' next to 'Implementation' text field.
Select 'Interface' tab
You should adjust the settings to following:
Format: Verilog
Vendor: Generic
Leave other options as default unless there is a reason that the
user want to adjust those.
Click on 'OK'
Make sure 'Produce Timing Simulation Data' is selected.
Click on 'OK' again to close 'Options'

Now you are ready to go.
NOTE: If you already have the design placed and routed, you can select the
specific design iteration in Design Manager and open up Flow Engine.
You do NOT have to re-run place and route just to generate a timing
simulation data. Just backup to the point right after Place and Route is
finished then click on forward button to re-generate simulation data in
'Timing' stage.




End of Record #2977

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals!

© 1998 Xilinx, Inc. All rights reserved
Trademarks and Patents