Answers Database

Foundation F1.3/F1.4, XABEL: Supported 'Xilinx Property' for CPLDs withXABEL6


Record #3020

Product Family:  Software

Product Line:  Data I/O

Problem Title:
Foundation F1.3/F1.4, XABEL:  Supported 'Xilinx Property' for CPLDs
withXABEL6



Problem Description:
Keywords:  abel, data i/o, abl2edif, cpld, plusasm, xepld

Urgency:  Standard

General Description:

What are the supported 'Xilinx Properties' with XABEL6 in
Foundation F1.3?


Solution 1:

The following Xilinx Properties are supported by the CPLD
EDIF-based flow for XABEL.  By default, Foundation F1.x XABEL
writes out EDIF netlists from the Abel source file.
If you have an existing XABEL design that contains XEPLD
PROPERTY (or PLUSASM PROPERTY) statements, you must either
replace these properties with the supported EDIF-compatible
properties listed below or you must use the Plusasm flow
described in (Xilinx Solution 2776).  If you are developing a
new XABEL CPLD design, DO NOT USE Plusasm based properties.


XILINX PROPERTIES AVAILABLE IN XABEL
====================================

You can specify the following attributes in your XABEL source
file using the ABEL "XILINX PROPERTY" statement:

XILINX PROPERTY 'INITIALSTATE [state_reg_signal] state_name';
    (Defines the initial state of a 1-hot encoded state
     machine.)
XILINX PROPERTY 'SAVE node_name...';
    (Preserves internal nodes; using ISTYPE 'KEEP' is
     preferred)
XILINX PROPERTY 'BLOCK {reg_signal | state_name}
     attrib_name[=attrib_value]';
    (Assigns arbitrary XACT-M1 attributes to registers in the
     design.)
XILINX PROPERTY 'OPTIMIZE {AREA | SPEED | BALANCE | OFF}';
    (Selects OPTX optimization strategy for FPGA XABEL
     modules.)
XILINX PROPERTY 'OPT_EFFORT {NORMAL | HIGH}';
    (Selects OPTX optimization effort for FPGA XABEL
     modules.)
XILINX PROPERTY '{FAST | SLOW} output_pin...';
    (Selects output slew rate for output pins in top-level
     XABEL design.)
XILINX PROPERTY 'BUFG={CLK | OE | SR} input_pin...';
    (Assigns global buffers to input pins in top-level XABEL
     design.)
XILINX PROPERTY 'IO reg_signal...';
    (Defines registers to be implemented in the IOBs.)
XILINX PROPERTY 'INIT={R | S} reg_signal...';
    (Defines initial state of registers.)
XILINX PROPERTY 'WIREAND node_name...';
    (Defines logic nodes to be implemented in the CPLD
     interconnect array.)
XILINX PROPERTY 'PWR_MODE={LOW | STD} signal_name...';
    (Selects macrocell power mode for nodes or outputs in
     CPLD designs.)
XILINX PROPERTY 'TNM=string signal_name...';
    (Tags signals with a Timing-group Name to be used in a
     Timespec.)

The following ABEL attributes are automatically forwarded to the Implementation
software via the EDIF netlist:

ISTYPE 'KEEP'
    (Preserves internal nodes in both ABEL compiler and
     design implementation.)
ISTYPE 'RETAIN'
    (Preserves redundant logic terms in both ABEL and design
     implementation.)

In addition, pin numbers specified in top-level XABEL designs are written to the
 EDIF netlist as LOC constraints for design
implementation.







End of Record #3020