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M1.3/M1.4: Verilog and VHDL SIMPRIM models for X_RAMD16 have only one output port


Record #3050

Product Family:  Software

Product Line:  Merged Core

Problem Title:
M1.3/M1.4: Verilog and VHDL SIMPRIM models for X_RAMD16 have only one
output port



Problem Description:
Keywords: ramd, ram, dual port, simprim, verilog, vhdl,

Urgency: standard

General description:
A dual port RAM has two output ports called
SPO (single port out) and DPO (dual port out), however
both the Verilog and VHDL SIMPRIM models for the Dual Port
RAM primitive (X_RAMD16) have only one output port, and
this may be a source of confusion at first glance.

For example, in the Verilog SIMPRIM library, the
X_RAMD16 port declaration shows only one output called "OUT":

  module X_RAMD16 (OUT, IN, CLK, WE, WADR0, WADR1, WADR2,
  WADR3, RADR0, RADR1, RADR2, RADR3);



Solution 1:


The X_RAMD16 in a post-NGDBUILD, post-Map, or post-route
netlist is only part of the model for a RAM16x1D Unified
Library component.

The dual output RAM16X1D component is actually modeled using
a *combination* of an X_RAMD16 and and an X_RAMS16 SIMPRIM
(single port Synchronous RAM) in back annotated simulation
netlists.

The main reason behind this is because the Xilinx M1
Implementation Tools require that all SIMPRIM (simulation
primitive models) have only ONE output pin.  In keeping
with this rule, the X_RAMD simprim has only a DPO (dual
port output) pin.  (Note, however, that it still has both read and write address
 ports.)

To achieve the full function of the RAM16X1D library element,
the X_RAMD simprim is wired in parallel with an X_RAMS
(single port sync RAM) simprim.  The X_RAMS simprim is used
to generate the SPO output of the RAM16X1D, using the write
address as its address input.


Reference #'s: 101771, 101772



End of Record #3050