Return to Support Page
 homesearchagentssupportask xilinxmap

Answers Database


M1.3/M1.4 CPLD: Fitter incorrectly trimming pin from macro which is driving multiple outputs


Record #3055

Problem Title:
M1.3/M1.4 CPLD: Fitter incorrectly trimming pin from macro which is
driving multiple outputs



Problem Description:
Keywords:  9500, CPLD, Hitop, trim, macro, vhdl, abel, hierarchy, fitter

Urgency:  Standard

General Description:

If you have multiple pins being driven by the same signal
inside a macro, and those pins in turn, drive output pins in
the top level schematic, the CPLD fitter will trim away all but one net coming o
ut of the macro. This is true for both
ABEL and VHDL macros.




Solution 1:

The current workaround for this issue is to have the signal drive multiple nets
outside of the macro instead of from inside
the macro.

In addition, add a buf to the signals which are being trimmed.
You would then have the macro pin going to a buf -> obuf -> opad
on the top level for the signal that was being trimmed.



End of Record #3055

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals!

© 1998 Xilinx, Inc. All rights reserved
Trademarks and Patents