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Foundation F1.3/F1.4, XC9500, XVHDL: Macro pass-through signals trimmed away or tied to VCC/GND.


Record #3076

Problem Title:
Foundation F1.3/F1.4, XC9500, XVHDL: Macro pass-through signals trimmed
away or tied to VCC/GND.



Problem Description:
Keywords: XVHDL, Metamor, macro, feedthrough

Urgency: standard

General Description:

When an XC9500 design contains an XVHDL (Metamor) macro and the
macro conatins pass-though signals (output ports directly
driven by input ports), the fitter (hitop) issues an nd14
warning indicating that the pass-though nets are not driven and
are being removed. The resulting implementation is logically
incorrect.


Solution 1:

In the macro's VHDL file, define an intermediate signal to pass
 the affected input through. Assign the input port to the new
signal and change the output port's assignment to refer to the
internal signal instead of the input port directly. Declare the
Metamor attribute "critical" on the signal as follows:

  attribute critical of DUMMY : signal is true;

You also need to declare the METAMOR library and use the
METAMOR.attributes package at the top of the VHDL file. This
will cause Metamor to insert a buffer between the input and
output ports in the macro's netlist which avoids the fitter
bug.

For example:
library METAMOR;
use METAMOR.attributes.all;
entity test is
   port (
	IN1 : in STD_LOGIC;
	OUT1 : out STD_LOGIC
	);
end test;
architecture test_arch of test is
signal DUMMY : STD_LOGIC;
attribute critical of DUMMY:signal is true;
begin
DUMMY <= IN1;
OUT1 <= DUMMY;
end test_arch;



Solution 2:

This solution applies when the top-level design is also an
XVHDL (Metamor) design. If the source design for the macro is
contained in the same file as the top-level entity that
instantiates the macro, you can instruct Metamor to flatten the
hierarchy, which avoids the problem. In the top-level
architecture, after the macro's component declaration, include
the Metamor attribute "ungroup" as follows:

  attribute ungroup : boolean;
  attribute ungroup of MYMACRO : component is true;

The Metamor library is not required for this attribute. No
further modification of the user design is required, making
this a less intrusive workaround. The use of the ungroup
attribute is described in the Metamor user guide in the online
help.

For example:
entity VHDL_MAC is
   port (IN1 : in STD_LOGIC;
	 OUT1 : out STD_LOGIC);
end VHDL_MAC;
architecture mac_arch of VHDL_MAC is
begin
OUT1 <= IN1;
end mac_arch;

entity TOP_LEVEL is
port (A : in std_logic;
      X : out std_logic);
end TOP_LEVEL;
architecture STRUCTURE of TOP_LEVEL is
component VHDL_MAC port (
	IN1 : in std_logic;
	OUT1 : out std_logic);
end component;
attribute ungroup : boolean;
attribute ungroup of VHDL_MAC:component is true;
begin
U1 : VHDL_MAC port map(
	IN1 => A,
	OUT1 => X);
end STRUCTURE;



End of Record #3076