Answers Database

M1.3/M1.4: Viewlogic board level simulation methodology


Record #3080

Product Family:  Software

Product Line:  ViewLogic

Problem Title:
M1.3/M1.4: Viewlogic board level simulation methodology


Problem Description:
Keywords: Viewsim, Viewdraw, board, chip, simulate, functional, timing

Urgency: Hot

General Description:
This solution record describes the flow required to run functional and timing
simulations for boards containing Xilinx devices.  As this has been written
by Xilinx, it will only cover the portions of the flow pertaining to the
Xilinx designs; for more information about the flow for other vendors,
contact Viewlogic or the vendor of the other devices being simulated.

This solution covers:
- Directory structure
- Project setup (Viewlogic)
- How to create chip level symbols
- Functional simulation
- Partial Timing simulation
- Other considerations

These instructions assume Workview Office is the Viewlogic tool used, but
Powerview can certainly be used as well.


Solution 1:

Project Directory Setup:

For the individual chip designs, it's business as usual.  Create the project
with the standard M1-Viewlogic libraries, compose the design as usual, and
process the design through the M1 toolset normally.  Remember, the Xilinx
tools know nothing about the board level, so nothing will be different about
how the individual designs are processed.

Next you will create a board level project directory.  You can use the same
viewdraw.ini file as the individual projects, although the family library
(i.e. xc4000ex) and LogiBLOX libraries should be removed.  Make sure you have
a primary library (DIR [p]) as well as the SIMPRIMS (this contains SIMulation
PRIMitiveS), builtin, and xbuiltin Xilinx libraries.  Include libraries
required by other chip vendors as necessary.



Export designs from the individual design projects to the board level project:

These four steps detail what must be done to bring the individual design
netlists to the board level project directory.	The sample command lines in
this Solution assume a design name of CHIP1.

The first two steps are part of the normal design implementation flow:

1) EDIFNETO -l xilinx chip1
2) NGDBUILD chip1.edn

At this point, you will have a chip1.ngd file.	To avoid overwriting the
original EDIF file, copy this file to the board level project directory
before continuing.

If you are using the Design Manager / Flow Engine to compile the design,
there will be an .NGD file in the "version" subdirectory that you can use,
although the name will be the family you are using (i.e. xc4000ex.ngd)
instead of "chip1.ngd".

The following two steps are run in the board level project directory:

3) NGD2EDIF -n -v viewlog chip1.ngd chip1.edn
4) EDIFNETI chip1.edn


Notes:

- If the chip design changes, these steps must be redone to update the
information in the board level design directory.

- The top level designs in each of the individual projects must be uniquely
named to avoid contention on the board level schematic.  Lower levels of
hierarchy can be duplicated safely.

- The -n option for NGD2EDIF is used to flatten the design; one wire file
will be created when EDIFNETI is run.  Without this option, numerous wire
files named XBA#.1 (the # is unique) will be created by EDIFNETI.  Given that
multiple Xilinx designs would produce conflicting XBA# files, the -n is a
requirement.



Creating the chip Symbol:

Now that you have a chip1.1 wire file in the board level project area, you
can create a symbol to represent that chip.  Viewlogic's ViewGen tool can
perform this function.

1)  Open the ViewGen utility and set the Input to CHIP.1.  Do not change the
output from the default CHIP.1, as any change here will break the connectivity
between symbol and wire files.

2)  Select "Generate Top Level Symbol" and de-select "Generate Schematic".

3)  Click on the "Advanced.." tab.  ViewGen does not automatically create bus
pins on the symbol, so you will have to enter the names of all the buses on
the chip.  Enter these (with no bounds, separated by spaces) in the "Bus Name"
field.	Leave all other fields blank.

4)  Click OK to leave Advanced, then click OK to generate the symbol.

For Powerview users, the command line equivalent for these options is:

viewgen <chip1> <chip1> -makesym -noschem -busname <BUS_IN BUS_OUT>

where the two references to "chip1" are input and output, respectively, and
"BUS_IN" and "BUS_OUT" are the names of buses connected to chip pins.
Everything in <> brackets will be unique to your design (and remove the <>).

Perform these steps for each chip design that you have brought into the board
level project area.

If the pinout of a chip changes, the symbol must change accordingly.  This
can be done by redoing all of the steps above (except the project creation
steps), or by simply modifying the existing symbol.  For most cases, the
latter will be easier, for regeneration of the symbol can totally change the
order and spacing of the symbol pins.



Completing the board level schematic:

Now that you have the symbols for the lower level chips, you can complete the
board level schematic.	Do not use any logic from the Xilinx libraries --
remember, this will only be used for simulation purposes.

It is possible to bring in the schematics from the individual chips to probe
these lower layers during simulation.  Simply copy the schematic and symbol
files (from the SCH and SYM folders) from the individual projects to the SCH
and SYM folders in the board level project.  You will need to add the
appropriate library listings in the viewdraw.ini to view these schematics.

A few caveats here:
1. Since everything is in one project, unique symbols/schematics with common
names will not be able to exist without unique aliases.  Be careful.

2. If you save the board level schematic with the underlying original
schematics present, you will overwrite the WIR files that you imported with
EDIFNETI.  This is very important to remember when doing the timing simulation
flow, as you would therefore overwrite the timing information brought in via
EDIF.


At this point, you are ready to simulate.  Choose Tools->Create Digital Netlist
from Workview Office ViewDraw, or create the VSM file via GUI or command line.
Simulate as usual.  Remember to toggle the global resets for all Xilinx
devices; see (Xilinx Solution 128) for more details.



Solution 2:

Timing Simulation:

It is possible to import EDIF with timing information into the board level
project.  Starting with the placed and routed .NCD file, run the following
three programs:

1) NGDANNO chip1.ncd chip1.ngm

This will produce CHIP1.NGA.  Copy this file to the board level project to
avoid overwriting the existing EDIF file with the next step.  If you are using
the Design Manager / Flow Engine and have selected "Produce Timing Simulation
Data", CHIP1.NGA will exist in the "revision" subdirectory.

2) NGD2EDIF -n -v viewlog chip1.nga chip1.edn

Because of the -n option (described above), you cannot use the TIME_SIM.EDN
file produced by the Flow Engine.  This will replace the existing chip1.edn
file (with no timing information) in the board level project directory.

3) EDIFNETI chip1.edn

This will update the wire file in the project directory with timing
information.


This flow will allow you to simulate the board with timing information for
the Xilinx chips, but will not include timing information for other devices
or the board itself.  That information is beyond the Xilinx scope; please
contact Viewlogic for more information.



Solution 3:

Other considerations:

If the Xilinx chip designs contain LogiBLOX or instantaited XNF, EDIF, etc.,
there is no problem because NGDBUILD will have merged all the modules into the
single .NGD file.

However, there is one case that requires special consideration.  If you have
ROM or RAM with initial values in your design, NGD2EDIF will produce an .XMM
file that will be used to initialize these components.	This .XMM file is
created with the single chip design as the top level, so it must be modified
before it can be applied to the board level schematic.

Copy this .XMM file along with the .NGD or .NGA file for the chip design into
the board level project directory.  Open the .XMM file in a text editor.  The
file will contain many lines that look like this:

LOADM $1I34\MEM0_0\X_R16 (0:0) 0\b


$1I34 in this example is the top level of the instance of the RAM/ROM
component.  This hierarchical path will need one more layer when placed in
the board level schematic.

After placing the Xilinx chip symbol on the board level schematic, double
click on it.  In the Component Properties box that opens, under the Name tab,
it will show something like (for our example): Component:  CHIP1.1 - $1I4
The name $1I4 will also be shown in the lower left corner of the schmatic
sheet when that block is selected.

This "$1I4" is the reference name that will be used to complete the hierarchy
listing.  Alternatively, you can fill in the Label field to give this block
a unique name.	The .XMM file must be modified accordingly.  Add the
hierarchical instance to the beginning of each instance:

LOADM $1I4\$1I34\MEM0_0\X_R16 (0:0) 0\b


Use the "execute" command to run this file at the beginning of your ViewSim
command file:

execute CHIP1.XMM

This must be done for each Xilinx chip that requires initialization of RAM/ROM.



End of Record #3080