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Xilinx (FPGA/CPLD) configuration run times (configuration rates/programming times)?


Record #3090

Problem Title:
Xilinx (FPGA/CPLD) configuration run times (configuration
rates/programming times)?



Problem Description:
Keywords: xc3000, xc4000e/ex, xc5000, xc9500

Urgency: Standard

General Description: What are the Xilinx configuration rates/programming
times for FPGAs and CPLDs?


Solution 1:

Any of the Xilinx FPGAs can be configured and reconfigured in several
different modes.  The fastest is called Slave Serial, where an external
clock is provided that shifts in the serial configuration data. Slave
Serial, which reduces the power-up delay, allows for an external clock
rate of 10 MHz maximum. Other modes can be up to 15 times slower.  The
following description doesn't include the power-up cycle of the FPGA.
For further details, read the resolution that covers the more
involved details and calculations (Power-on delay).

In configuration modes that use the internal CCLK such as Master Serial, the int
ernal CCLK is subject to variations with process, temperature and power supply.
In older Xilinx families (XC3000A family) the serial datastream rate is limited
to this internal 1 MHz, in the newer families ( XC4000 and XC5200 families ) it
is selectable between 1 MHz (nominal) and 8 MHz (nominal) rate (using the fast c
onfiguration mode), and can be driven at up to 10 MHz. In the default slow mode,
 the frequency ranges from 0.5 MHz to 1.25 MHz.  In the fast CCLK mode, the freq
uency ranges 4 MHz to 10 MHz.

The number of bits varies with device size: 14,779 bits for the smallest XC3000
device (XC3020) to 5,433,888 bits for the presently largest XC4000 device (XC402
50XV).

To use the internal 8 MHz (nominal) CCLK:

5.2.x : makebits -f ConfigRate:Fast  design.lca
M1.x  : bitgen -g ConfigRate:Fast   design.ncd

Note: The XC3000 doesn't offer this option
Note: That comes to 10 to 20 bits per gate

Configuration times are thus between 10 ms and 544 ms, if you use the
faster clock rate for the bigger devices. Byte-parallel configuration
modes are not any faster, since they operate byte-to-serial conversion
within the chip. The exception is the XC5200 Express mode that accepts
byte-wide date at 10 MHz, thus configuring the XC5215 with 237,744 bits
in about 4 ms.



Solution 2:

There is an app note discussing xc9500 programming times which is
available at http://www.xilinx.com/xapp/xapp068.pdf



Solution 3:

Here are the more involved details and calculations (XC3000, 4000E/EX and 5200):


1.  The FPGA becomes active internally at about 3.5 volts.  For the XC4000, ther
e is a built-in power-on delay that waits an additional 64 ms for power to all t
he devices on the board to become stable (it's only 16 ms if the FPGA is configu
ring in peripheral or slave mode).  For the XC5200 devices, there is no distinct
ion between master and slave modes with regard to the power-on delay.  A power-o
n delay of 4 ms (nominal) is applied in the XC5200 family of devices.  When all
the /INIT pins are tied together in daisy chain configuration, as recommended, t
he longest delay takes precedence.  When daisy-chaining a XC3000 device, the /RE
SET signal, which is used in XC3000 to delay configuration, should be connected
to the /INIT.  For XC3000, master mode configurations have a power-on delay of 4
3 to 130 ms.  While other non-master modes for the XC3000 have a power-on delay
of 11 to 33 ms.

2.  After the power-on delay expires, the internal configuration memory is clear
ed. This requires ~1.3 us per data frame. The number of frames can be obtained f
rom the Programmable Logic Data Book.

3. A XC4000 or XC5200 device configured in master mode waits an additional 32 to
 258 us before re-sampling the /INIT and the configuration mode pins. Use the 25
8 us value or 0.258 ms as worst case value.  The XC3000 samples the mode pins (2
 us).

4.  The next step is to load the configuration data into the device.
If the fast configuration mode is used plus a serial PROM that supports
it (i.e. XC17128D or XC17256D), then the FPGA configures up to 8 times
faster than if you use the standard serial mode.  The first few bits are shifted
 in at the slow rate until the enable bit is encountered. Once enabled, the FPGA
 will shift its configuration data in at between 4 MHz to 10 MHz.  Again, Use th
e worst-case value of 4 MHz corresponding to 0.25 us per bit.  The number of bit
s can be obtained from the Programmable Logic Data Book.  Multiplying 247,960 ti
me 0.25 us per bit.  The first few bits are slower, so make a conservative estim
ation to the overall loading.  For XC3000 devices, you should use XC3000 CCLK as
 1 MHz (nominal) since you do not have the option of selecting a fast CCLK.

So from the time that Vcc > 3.5 volts to a configured FPGA device should be:

Power-On Delay		   (Step 1):	 x ms
Clear Configuration Memory (Step 2):	 x ms
Master Mode /INIT Delay    (Step 3):	 x ms
Load Configuration Data    (Step 4):	 x ms
------------------------------------	---------
TOTAL					 x ms

Note: Add a 30% guardband above the worst-case values to cover the time
the power supply takes to go between 0 and 3.5 volts.

Some other caveats:

Unless the fast serial configuration mode is enabled, the configuration
times could be up to 8 times longer.   You can reduce the configuration
times by setting the CCLK frequency.

Larger devices have more data frames and more program bits and will take a corre
spondingly longer time to configure.



End of Record #3090