Answers Database

PCI Core Generator 2.0: Verilog synthesis/simulation with PCI LogiCORE v2.0, FPGA Compiler v1997.08, VerilogXL v2.5, and M1.3.7


Record #3099

Product Family:  Software

Product Line:  Logicore

Problem Title:
PCI Core Generator 2.0: Verilog synthesis/simulation with PCI LogiCORE
v2.0, FPGA Compiler v1997.08, VerilogXL v2.5, and M1.3.7



Problem Description:
Keywords: PCI, LogiCORE, FPGA Compiler, Cadence, VerilogXL, 1997.08, 97a,
2.5,2.0, Verilog, M1.3.7

Urgency: Standard

General Description:

The PCI LogiCORE v2.0 can be implemtend in the Verilog synthesis/simulation
flow in M1.3.7, using Synospys FPGA Compiler v1997.08 and VerilogXL 2.5.

In this example, a design called 'ping' is used to demonstrate using the
PCI LogiCORE v2.0 in this Verilog synthesis/simulation flow.  In a 'real'
design, the 'ping' design is replaced with the customer application. The
PCI LogiCORE v2.0 comes with example files for compiling an initiator or target
with the 'ping' design.  The example used in this solution uses the initiator
with the ping design.

Note, it is asummed that the user has already setup the environment with
M1.3.7, Synopsys v1997.08, and VerilogXL v2.5.	Other versions of Synopsys and
VerilogXL can be used, as long as they are compatible with M1.3.7.


Solution 1:

Functional Simulation with Verilog XL v2.5.

(1) Download the PCI LogiCORE v2.0 core from the Xilinx PCI Lounge.  'unzip' or
gunzip the contents into a directory.  For this example, it is assumed that the
user has unpacked the contents of the core into the root directory of the
system.  This will create a directory called 'pcim', which contains the user's
configured PCI core and the verilog files needed to process this design.

(2) Setup your environment to run M1.3.7, Synopsys, and VerilogXL.

(3) cd pcim/verilog/example/func_sim

(4) The 'func_sim' directory will contain the two files ping_tb.f and
waves.wrf.  ping_tb.f names nine files that VerilogXL needs to functionally
simulate 'ping' with the PCI LogiCORE v2.0.  The nine files are:

../source/ping_tb.v	  -This is the testbench file for the design pci_top
../source/stimulus.v	  -A file used for signal generation in the testbench
../source/dumb_target.v   -A file used for signal generation in the testbenc
../source/dumb_arbiter.v  -A file used for signal generation in the testbenc
../source/pcim_top.v	  -The top-level design file which instantiates the
			   PCI LogiCORE and the user applications (e.g. ping)
../source/ping.v	  -The user application used with the PCI LogiCORE
../source/cfg.v 	  -Configuration file for the PCI LogiCORE
../src/xpci/pcim_lc.v	  -Verilog simulation model for the PCI LogiCORE
../src/xpci/pci_lc_i.v	  -Verilog simulation model for the PCI LogiCORE

The *.f file can be modified to perform functional simulation with another
design in place of 'ping'.  For functional simulation, the files pcim_top.v,
pcim_lc.v, pci_lc_i.v, and cfg.v must be used. The ping_tb.f file also contains
a pointer(-y) to the VerilogXL simulation models in M1.3.7.

pcim_top.v contains the instantiation of the the PCI LogiCORE.

pcim_lc.v contains the functional simulation model generated by the PCI Core
Generator.  Any time the core is modified an new model must be generated.

pci_lc_i.v contains the simulation library that allows the PCI LogiCORE to be
functionally simulated with VerilogXL.

cfg.v is a configuration file for setting various options within the PCI
LogiCORE.

Note, if your user design contains any instantiations of FFs, OBUFs, and/or
OBUFTs, functional simulation is only possible post-ngdbuild.

(5) To run the VerilogXL simulation, type at the unix prompt in the func_sim
directory:

verilog -f ping_tb.f

VerilogXL will proess the simulation files and return control to the user.

A directory called 'waves.wfm' which contains the waveforms of the functional
simulation.  simwave can be used to view the contents of 'waves.wfm'.



Solution 2:

Synthesis and Place & Route of a design with the PCI LogiCORE v2.0 using FPGA
Compiler v1997.08

(1) Using the 'pcim' directory structure, synthesis with FPGA Compiler is
performed in the 'synthesis' directory.  Go to the synthesis directory by
running the following command from your root directory:

cd pcim/verilog/example/synthesis

(2) The 'synthesis' directory will contain the WORK directory, the compile
script synopsys.dc, and the .synopsys_dc.setup file.  Modify the
.synopsys_dc.setup file for your system.  Do not modify the link_library and
target_library settings in the .synopsys_dc.setup file.

If you need to use the 4062XLT, delete the link_library, target_library,
symbol library, and synthetic_library settings.  Replace them with the 4062xl
equivalents by running:

synlibs -fc 4062xl-1

(3) Open the synopsys.dc file in a text editor of your choice.	There are six
items to notice.  These are items that must be followed when compiling a user
design with the PCI LogiCORE.


   (a) The compile script reads in an 'empty' Verilog file.
   Starting from the 'synthesis' directory, the file ../../src/xpci/pcim_lc.v
   is read into Synopsys.  This file contains no logic.  It only describes the
   pin directions of the PCI LogiCORE.	This file must be read into Synopsys
   so the netlist writer from Synopsys can write out the correct pin
   directions.	For any customer design, this file must be read into Synopsys.

   (b) ../source/cfg.vhd is read into Synopsys.
   cfg.vhd contains options for the PCI LogiCORE v2.0 that the use can specify.
   The cfg.vhd file must always be used.

   (c) A 'dont_touch' is placed on the instantiated PCI LogiCORE.
   A 'dont_touch' attribute must always be placed on the instantiation of the
   PCI LogiCORE.  The 'dont_touch' insures that the LogiCORE is not deleted
   by Synopsys.

   (d) Only some I/O cells are inserted into the design.
   In a normal synthesis design where the code is pure RTL, the following two
   commands are exectued to insert the correct I/O cells (IBUF, OBUF, IFD,
   etc.) on top-level ports:

   set_port_is_pad "*"
   insert_pads

   The PCI LogiCORE already has I/O cells present on some of its ports.
   Executing set_port_is_pad/insert_pads the normal way would create a
   syntactically incorrect netlist.  To avoid this problem, do not insert I/O
   on ports that already have a I/O cell.  set_port_is_pad can be selectively
   used on ports.  In the ping example, there are only two ports in the design
   that need I/O cells inserted:

   set_port_is_pad {PING_REQUEST, PING_DONE}
   insert_pads

   (e) Always use the pcim_lc.sxnf wrapper file.

   The last command in the synopsys.dc script copies a file called
   pcim_lc.sxnf.  This file is a wrapper which contains constraints needed to
   correctly use the PCI LogiCORE.  This procedure must always be followed.

   (f) Remove the place holder PCI LogiCORE design from Synopsys memory.

   The pcim_lc.v file contains no logic.  pcim_lc.v is only used to get the
   correct pin directions for the netlist writer.  This design must be
   'removed' from the FPGA Compiler memory just before writing out the design.
   If it is not removed, an empty SXNF file will be created.  This empty SXNF
   file will remove the entire PCI LogiCORE when the design is processed by
   XACT.  This procedure must always be followed.

Close the synopsys.dc file.

(5) Synthesisze the design by running the synopsys.dc file from the Design
Analyzer GUI, or by using dc_shell:

dc_shell -f synopsys.dc |tee run.log

It is highly recommended that the Design Analyzer GUI be used.	The Design
Analyzer GUI will stop if an error in synthesis happens.  In contrast, the
dc_shell method will not stop if there is an error during synthesis.

(6) After synthesis of the design is complete, prepare to place and route by
cd'ing to the following directory:

cd pcim/vhdl/example/m1

The src directory contains the script run_m1.

(7) Open the file run_m1 in a text editor.  There are four items to note before
running this script.

   (a) User constraints must be placed in the m13xp208.ucf file.
   (b) The guide file m13xp208.ncd must be always be used.
   (c) Always use the XIL_MAP_LOC_CLOSED option.
   (d) Alwasy use the options specified for map and par.

(8) Place and route the design by running run_m1 in the m1 directory.



Solution 3:

Timing Simulation with VerilogXL v2.5

(1) After place and route of the PCI LogiCORE, cd into the post_sim directory:

cd pcim/verilog/example/post_sim

(2) The post_sim directory will contain 4 items, the ping_tb.f file, the
waves.wrf file, the structural Verilog file pci_top_routed.v, & the sdf file
produced by ngd2ver.  The ping_tb.f file contains the files that must be
processed for timing simulation of the PCI LogiCORE design.  The ping_tb.f
file contains six items:

../source/ping_tb.v	  -Testbench file for the design.
../source/stimulus.v	  -A file used for signal generation in the testbench
../source/dumb_target.v   -A file used for signal generation in the testbench
../source/dumb_arbiter.v  -A file used for signal generation in the testbench
..pcim_top_routed.v	  -Structural Verilog file produced by ngd2ver -y ...
+libext+.vmd		  -Path to the Verilog simualtion models in M1.3.7

Modify the path for the -y option for the path in your setup.

The ping_tb.f file can be modified to perform timing simulation with another
design in place of 'ping'.  For timing simulation, the file io_ff_fix.v must
always be used.

(2) Setup your environment to run M1.3.7 and VerilogXL v2.5.

(3) To run VerilogXL for timing simulation, type at the unix prompt in the
time_sim directory:

verilog -f ping_tb.f

VerilogXL will process the simulation files and return control to the user.
A directory called 'waves.wfm', which contains the waveforms of the timing
simulation, is created.  Use viewsim to view the contents of 'waves.wfm'.



End of Record #3099