Answers Database

PCI Core Generator 2.0: VHDL synthesis/simulation with PCI LogiCORE v2.0, FPGA Compiler & VSS v1997.08, and M1.3.7


Record #3103

Product Family:  Software

Product Line:  Logicore

Problem Title:
PCI Core Generator 2.0: VHDL synthesis/simulation with PCI LogiCORE
v2.0, FPGA Compiler & VSS v1997.08, and M1.3.7



Problem Description:
Keywords: PCI, LogiCORE, FPGA Compiler, VSS, 1997.08, 2.0, M1.3.7, VHDL

Urgency: Standard

General Description:

The PCI LogiCORE v2.0 can be implemented in the VHDL synthesis/simulation
flow in M1.3.7, using Synospys FPGA Compiler and VSS v1997.08.

In this example, a design called 'ping' is used to demonstrate using the
PCI LogiCORE v2.0 in this VHDL synthesis/simulation flow.  In a 'real' design,
the 'ping' design is replaced with the customer application. The PCI LogiCORE
v2.0 comes with example files for compiling an initiator or target with the
'ping' design.	The example used in this solution uses the initiator with the
ping design.

Note, it is asummed that the user has already setup the environment with
M1.3.7, & Synopsys v1997.08.  Other versions of Synopsys can be used, as long
as they are compatible with M1.3.7.


Solution 1:

Functional Simulation with VSS v1997.08

(1) Download the PCI LogiCORE v2.0 core from the Xilinx PCI Lounge.  'unzip' or
gzip the contents into a directory.  For this example, it is assumed that the
user has unpacked the contents of the core into the root directory of the
system.  This will create a directory called 'pcim', which  contains the user's

configured PCI core and the verilog files needed to process this design.

(2) Setup your environment to run M1.3.7 and Synopsys v1997.08.

(3) cd pcim/vhdl/example/func_sim

(4) The 'func_sim' directory contains 7 items:

WORK		-Directory used by VSS by processing a design
analyze_ping	-script that analyzes VHDL files for functional simulation
ping_include	-command file to the vhdlsim/vhdldbx tool
ping_traces	-command file which lists the signals to display for simulation
ping_wfc	-command file that sets display values for waveforms
run_ping	-script which runs functional simulation

in the case where 'ping' is replaced by a user design, all of the above files
would need to be modified.  Take note of the contents of analyze_ping, since
there are files in analyze_ping that must always be used.

By default, analyze_ping contains the following files:

../../src/xpci/pci_lc_i.vhd -VHDL functinoal VHDL sim model for the PCI
			     LogiCORE v2.0
../../src/xpci/pcim_lc.vhd  -Functional VHDL sim model of PCI LogiCORE v2.0
../source/cfg.vhd	    -VHDL file for setting options in PCI LogiCORE v2.0
../source/ping.vhd	    -User application
../source/pcim_top.vhd	    -Top-level VHDL file which connects core to 'ping'
../source/dumb_target.vhd   -Simulation signal generation file for testbench
../source/dumb_arbiter.vhd  -Simulation signal generation file for testbench
../source/stimulus.vhd	    -Simulation siganl generation file for testbench
../source/ping_tb.vhd	    -testbench

At a minimum, pci_lc_i.vhd, pcim_lc.vhd, & cfg.vhd must always be used by the
user. If the user design contains any instantiations of FFs, OBUFs, and/or
OBUFTs, then functional simulation must be performed post-ngdbuild.


(5) Copy a .synopsys_vss.setup file into the func_sim directory.  At a minimum,
make sure that the XC4000E and SIMPRIM path in the .synopsys_vss.setup file has
the correct path for your setup.  The path for the XC4000E library must point
to the M1.3.7 VSS XC4000E simulation libraries.  The path for the SIMPRIM
library muyst poiint to the M1.3.7 VSS SIMPRIM(VITAL) libraries.

(6) To run the functional simulation, first run the script analyze_ping.  Next,
run the script run_ping.  If run_ping is successful, a waveform window will
appear and the vhdlsim prompt '#' will appear.



Solution 2:

Synthesizing/Place & Route the PCI LogiCORE v2.0 with FPGA Compiler v1997.08

(1) Using the 'pcim' directory structure, synthesis with FPGA Compiler is
performed in the 'synthesis' directory.  Go to the synthesis directory by
running the following command from your root directory:

cd pcim/vhdl/example/synthesis

(2) The 'synthesis' directory will contain the WORK directory, the compile
script synopsys.dc, and the .synopsys_dc.setup file.  Modify the
.synopsys_dc.setup file for your system.  Do not modify the link_library and
target_library settings in the .synopsys_dc.setup file.  If you need to use the
4062XLT, delete the link_library, target_library, symbol library, and
synthetic_library settings.  Replace them with the 4062xl equivalents by
running:

synlibs -fc 4062xl-1

(3) Open the synopsys.dc file in a text editor of your choice.	There are four
items to notice.  These are items that must be followed when compiling a user
design with the PCI LogiCORE.

   (a) ../source/cfg.vhd is read into Synopsys.
   cfg.vhd contains options for the PCI LogiCORE v2.0 that the use can specify.
   The cfg.vhd file must always be used.

   (b) A 'dont_touch' is placed on the instantiated PCI LogiCORE.
   A 'dont_touch' attribute must always be placed on the instantiation of the
   PCI LogiCORE.  The 'dont_touch' insures that the LogiCORE is not deleted
   by Synopsys.

   (c) Only some I/O cells are inserted into the design.
   In a normal synthesis design where the code is pure RTL, the following two
   commands are exectued to insert the correct I/O cells (IBUF, OBUF, IFD,
   etc.) on top-level ports:

   set_port_is_pad "*"
   insert_pads

   The PCI LogiCORE already has I/O cells present on some of its ports.
   Executing set_port_is_pad/insert_pads the normal way would create a
   syntactically incorrect netlist.  To avoid this problem, do not insert I/O
   on ports that already have a I/O cell.  set_port_is_pad can be selectively
   used on ports.  In the ping example, there are only two ports in the design
   that need I/O cells inserted:

   set_port_is_pad {PING_REQUEST, PING_DONE}
   insert_pads

   (d) Always use the pcim_lc.sxnf wrapper file
   The last command in the synopsys.dc script copies a file called
   pcim_lc.sxnf.  This file is a wrapper which contains contraints needed to
   correctly use the PCI LogiCORE.  This procedure must always be followed.

Close the synopsys.dc file.

(5) Synthesisze the design by running the synopsys.dc file from the
Design Analyzer GUI, or by using dc_shell:

dc_shell -f synopsys.dc |tee run.log

It is highly recommended that the Design Analyzer GUI is used.	The Design
Analyzer GUI will stop if an error in synthesis happens.  The dc_shell method
does not stop if an error occurs during synthesis.

(6) After synthesis of the design is complete, prepare to place and route by
cd'ing to the following directory:

cd pcim/vhdl/example/m1

The src directory will contain the script run_m1.

(7) Open the file run_m1 in a text editor.  Ther are four items to note before
running this script.

   (a) User constraints must be placed in the m13xp208.ucf file.
   (b) The guide file m13xp208.ncd must be always be used.
   (c) Always use the XIL_MAP_LOC_CLOSED option.
   (d) Always use the options specified for map and par.

(8) Place and route the design by running run_m1 in the m1 directory.



Solution 3:

Timing Simulation with VSS v1997.08

(1) After place and route is finished, cd to the post_sim directory:

cd pcim/vhdl/example/post_sim

(2) Copy into the time_sim directory the .synopsys_vss.setup file used for
functional simulation.	If functional simluation was not performed, the
.synopsys_vss.setup file used must, at a minimum, point to the SIMPRIM (VITAL)
simulation libraries. Use the file $XILINX/synopsys/example/template.synopsys_vs
s.setup as a template.

(3) After place and route is finished, the post_sim directory will contain the
following items:

.synopsys_vss.setup   -file created in step (2) above
WORK		      -directory used by Synopsys during timing simulation
analyze_ping	      -script analyzing VHDL files for functional simulation
ping_include	      -command file to the vhdlsim/vhdldbx tool
ping_traces	      -command file listing the signals displayed in simulation

ping.wfc	      -command file that sets display values for waveforms
run_ping	      -script which runs timing simulation
pcim_top_routed.vhd   -strucutral VHDL file created by ngd2vhdl
pcim_top_routed.sdf   -SDF file created by ngd2vhdl

In the case where 'ping' is replaced by a user design, some of the files above
need modification.  Take note of the contents of analyze_ping.	By default,
analyze_ping contains the following references:

../source/pcim_top_routed.vhd  -strucutral VHDL file produced by xnf2vss
../source/dumb_target.vhd      -simulation signal generator for testbench
../source/dumb_arbiter.vhd     -simulation signal generator for testbench
../source/stimulus.vhd	       -simulation signal generator for testbench
../source/ping_tb.vhd	       -testbench

(4) To run timing simulation, first run the script analyze_ping.  Next, run the
script run_ping.  IF run_script is succesful, a waveform window will appear and
the vhdlsim prompt '#' will appear.



End of Record #3103