Answers Database

NGDANNO: Problems with timing simulation not matching functional simulation, outputs stuck at X or 0


Record #3117

Product Family:  Software

Product Line:  Merged Core

Problem Title:
NGDANNO:  Problems with timing simulation not matching functional
simulation, outputs stuck at X or 0



Problem Description:
Keywords:  verilog, vhdl, backannotation, ngm, ngdanno, trce,
timing

Urgency: standard

General Description:
Problems have been observed in which the design outputs
in timing simulation do not match what is observed during
functional simulation.	Outputs may be stuck at X or "0",
even though the simulation is run at a clock frequency that is
well within what TRCE estimates the design can run at.


Solution 1:

The problem is associated with a bug seen when the NGM file
is specified as an input to NGDANNO.


WORKAROUNDS:
-----------
In command line mode, the workaround is to omit the NGM
file when running NGDANNO.

If you are running Design Manager, deselect the option,
"Correlate simulation netlist with input design".


The problem is fixed in x1_4.12.



End of Record #3117