Answers Database

XC9500: How are inital states of flip-flops determined on the 9500 CPLD's?


Record #3123

Problem Title:
XC9500: How are inital states of flip-flops determined on the 9500
CPLD's?



Problem Description:
keywords: initial, init, CPLD, 9500, powerup, state

Urgency: Standard

General Description:
The user may want to have the powerup state of a flip flop to be a logic high -
`1`. What type of flip flop would have to be used in
order to achieve that? Is there a property that can be attached to
a flop to have it powerup into a `1` state? What happens if the
flop has a preset and a clear?


Solution 1:

Having the flop FDP in the design will power up in the `1` state,
where as having flops such as FD or FDC will power up in the `0`
state. But adding the attribute INIT=S will allow ANY flip-flop
with this attribute to power up in the `1` state.

The only special case is with the FDCPE, since it has a preset and
a clear. If the clear signal is asserted, it will override the
preset, and upon power up will come up in the `0` state, but if
the attribute INIT=S is attached to this flip-flop, then the flop
will indeed power up in the `1` state.

Similarly, attaching an INIT=R attribute on an FDP will bring it
up in `0` state.




End of Record #3123