Answers Database

TAENGINE M1.3: ERROR:hi402 there is no original clock signal to clock pin *.CLKF


Record #3142

Product Family:  Software

Product Line:  EPLD Core

Problem Title:
TAENGINE M1.3: ERROR:hi402 there is no original clock signal to clock
pin *.CLKF



Problem Description:
Keywords:  taengine, cpld, 9500, m1.3, hi402, error

Urgency:  standard

General Description:

Customer has a cpld design that they want to produce timing sim data for.  In m1
.3 the design will translate and fit with no problems.	But then the taengine is
 executed and right away the flow engine stops and the design manager will repor
t that the deign was timed with errors.  If you open the timing report it is bla
nk.  The last line of the fe.log is  :

taengine -f design -l design.tim


Solution 1:

This error has been found in the M13.7 release with all the latest patches, howe
ver the problem has been fixed in the M1.4
release.



End of Record #3142