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M1.4 NGD2VER: How to have M1 automatically specify the addition of the `uselib directive and path to the simulation netlist


Record #3167

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
M1.4 NGD2VER: How to have M1 automatically specify the addition of the
`uselib directive and path to the simulation netlist



Problem Description:
Keywords: ngd2ver, uselib, libext, verilog, simulation libraries, -y, +libext

Urgency: Standard

General Description:  When performing a timing simulation with Verilog XL,
you must specify the location of the simulation libraries in order to
perform the simulation.  There are typically three methods in which you
may do this.  The resolutions below explain these three options.



Solution 1:


You may have the M1 Verilog simulation netlister, ngd2ver, automatically
specify the `uselib directive by using the -ul commandline switch.

If using the M1 tools from the command line, simply add the -ul switch when
envoking ngd2ver:

ngd2ver -ul <other_options> time_sim.nga

This will add the following line to the Verilog
simulation netlist from M1:

`uselib <path_to_xilinx>/verilog/data libext=.vmd

If you are using the Design Manager GUI to implement the design.  This switch
may be added by performing the following steps:


1. From the Utilities pull-down menu in the Design Manager,
   select Template Manager.

2. Select the New button and give your custom template a name, such as Verilog.

3. Select your template from the Template window and press the
   customize button.

4. Within the Custom Template Dialog Window is where you can
   specify the -ul switch for ngd2ver by typing ngd2ver in the
   "Program Name" box and -ul in the "Program Options" box.

   (WEBIMAGE 1:Template Manger Window)

5. Hit the Set Button on the Template Custom Options menu and then
   hit the OK button and exit the Template Manager by clicking
   the Close button.

6. Implement the design.  Before running the implementation,
   select the "Options" button, then the Implementation "Edit
   Template..." Button.  Select the Interfaces Tab from the
   Implementation Options window.  Under Simulation Data Options,
   select Verilog as the netlist format.  Select OK.

   (WEBIMAGE 2:Design Manager Implementation Options Window)

7. From the Options window, select your newly created
   template in the Implementation field of the Design
   Implementation Options window.  Then select the
   "Produce Timing Simulation" radio button.  Once
   this is done, you are ready to run the design.

   (WEBIMAGE 3:Design Manager Options Window)




Solution 2:

You may also specify the library directory and extenstion from the
commandline wher envoking Verilog-XL with the -y and +libext switches:

    verilog -y <path_to_xilinx>/verilog/data +libext+vmd testbench.v timesim.v




Solution 3:

As a last resort, you may also manually add the `uselib directive to the
begining of the Verilog simulation netlist:

    `uselib <path_to_xilinx>/verilog/data libext=.vmd



End of Record #3167