Answers Database

Foundation F1.3, XVHDL 3.0.2/3.0.3: Using a dedicated input pad for an instantiated global buffer (bufg)


Record #3174

Product Family:  Software

Product Line:  Metamor

Problem Title:
Foundation F1.3, XVHDL 3.0.2/3.0.3: Using a dedicated input pad for an
instantiated global buffer (bufg)



Problem Description:
Keywords: XVHDL, Metamor, attribute, pinnum, global, buffer,
	  bufg

Urgency:   Standard

General Description:

Typically, when you want to use a dedicated input pad for
an instantiated global buffer, you must use the 'inhibit_buf'
attribute on the input signal port to prevent XVHDL from
inserting an IBUF at the input.


--Example of instantiating a global buffer with dedicated pad

library IEEE;
use IEEE.std_logic_1164.all;

library METAMOR;
use METAMOR.attributes.all;


entity USE_BUFG is
   port (CLK, IN1: in std_logic;
	 OUT1: out std_logic);


   attribute pinnum of CLK  : signal is  "P124";
				--lock CLK to P124

   attribute inhibit_buf:  boolean;
			      --declare the attribute
   attribute inhibit_buf of CLK: signal is true;
      --This attribute prevents XVHDL from inferring an IBUF
      --on the CLK port, which allows the Xilinx software to
      --use the dedicated clock input pin.
end USE_BUFG;

architecture TEST of USE_BUFG is
   signal BUFG_OUT: std_logic;
   component BUFG
      port (I: in std_logic;
	    O: out std_logic);
   end component;

begin

   U1: BUFG port map (I => CLK, O => BUFG_OUT);

   process (BUFG_OUT)
   begin
      if (BUFG_OUT'event and BUFG_OUT='1') then
	 OUT1 <= IN1;
      end if;
   end process;

end TEST;


Sythesizing this example with Metamor versions
3.0.2/3.0.3 (Foundation F1.3/Performance Pack Update),
however, will not properly use the 'attribute pinnum'
to lock down to a specific dedicated input pad.




Solution 1:

The above mentioned Metamor compiler versions incorrectly
place the 'attribute pinnum' on the buffer and not the pad
itself.  Thus, when using the 'inhibit_buf' attribute
in conjunction with 'attibute pinnum', the pin lock is
not reflected in the <design>.edn file.

The workaround is to lock down the pin in the <design>.ucf
file and NOT the VHDL source code.

--Example of syntax in <design>.ucf file

NET clk LOC = P124;

Note that it is not absolutely necessary to lock the pin down
to a specific dedicated pin.  If you do not apply the LOC
constraint, the compiler will simply choose one of the 4
dedicated global buffer pads to use.  If you wish to tell the
compiler WHICH of these 4 pads to use, then you must place the
LOC constraint in the UCF file as described above.

*NOTE: This issue has been resolved in Foundation F1.4




End of Record #3174