Answers Database

COREGEN, VERILOG: How to do functional and backannotated timing simulation of designs with COREGen modules in M1


Record #3193

Product Family:  Software

Product Line:  Coregen

Problem Title:
COREGEN, VERILOG:  How to do functional and backannotated timing
simulation of designs with COREGen modules in M1



Problem Description:
Keywords:  Verilog simulation, ngd2ver

Urgency:  standard

General Description:
Verilog simulation of designs containing CORE Generator
modules in the Xilinx M1.4 release is supported by

  - the NGD2VER netlister, and
  - the Verilog SIMPRIM libraries.




Solution 1:

Functional simulation:
----------------------
Currently there are no behavioral Verilog simulation models
available for the Xilinx CORE Generator cores.
Functional simulation must be performed on a post-NGDBUILD
database.

Steps:

1. Merge all the XNF, (.sxnf,) EDIF and NGO files that
comprise your design by running NGDBUILD on the top level
file:

  ngdbuild <top>


2. Generate a Verilog simulation netlist by running NGD2VER
on the NGD file:

   ngd2ver -tf <top>.ngd

If you are using Cadence Verilog-XL, it is also helpful to
include the -ul option, which will give you a .v file with a
`uselib instruction embedded in it.  This directive points to
your M1 Verilog SIMPRIM simulation library.

For all other third party Verilog simulators, you must point
explicitly to the Verilog SIMPRIM libraries, which are located
in:

  $XILINX/verilog/data





Solution 2:

Timing simulation:
------------------
Timing simulation can be performed at two different points
of the flow:

  - post-Map  (after logic mapping to CLBs)
  - post-PAR  (after place and route)

Post-Map timing simulation gives you a rough estimate of
whether your design can meet your performance requirements
in the absence of routing delays.  If your design does not
meet timing in a post-Map timing simulation, it will never
meet timing after the additional delays associated with
routing are added on.


Post-MAP timing simulation
--------------------------
To run post-Map timing simulation, perform the following steps
after NGDBUILD (command line mode):

  map <top>[.ngd]
  ngdanno <top>[.ngd]  <top>.ngm
  ngd2ver -tf <top>[.nga]

For Verilog-XL:  specify the -ul option when running NGD2VER:

  ngd2ver -ul -tf <top>[.nga]


Edit a copy of the .tv file (testbench template), adding
your test vectors to it, then run your simulation.



Post-PAR timing simulation
--------------------------
Post-PAR timing simulation models the timing behavior of the
fully placed and routed design.

To run post-PAR timing simulation, perform the following steps
after MAP:

  par <top> <outputfile_name>
  ngdanno <outputfile_name>.[ncd]
  ngd2ver <outputfile_name>.[nga]

For Verilog-XL, include the -ul option when running NGD2VER:

  ngd2ver -ul -tf <outputfile_name>[.nga]

Edit a copy of the .tv file (testbench template), adding
your test vectors to it.



NOTE:
-----
When running the simulation, you must specify the testbench
file first on your command line:

Example (Verilog-XL, assuming that the testbench is named
test.stim, and the design is called "test"):

  verilog test.stim test.v



End of Record #3193