Answers Database

Foundation F1.4 Simulator, XC3000: Outputs are undefined in Timing Simulation


Record #3219

Product Family:  Software

Product Line:  Aldec

Problem Title:
Foundation F1.4 Simulator, XC3000: Outputs are undefined in Timing
Simulation



Problem Description:
Keywords:  undefined, initialize, unknown, simulate, GR, reset

Urgency:  Standard

When running a Timing Simulation of a 3K device in Foundation
1.4 the outputs of the simulation are undefined.


Solution 1:

The first cause of this is that the registers are not getting
initialized properly.  There is a signal called GR in the
simulation netlist which simulates the power-on global reset.
This GR signal must be toggled at the start of the simulation
in order to properly initialize the simulation.

To drive this GR signal:
Select Signal -- Add Signals. Then double click on the GR
signal. Now apply a stimulas to the signal and Toggle. Hold it
low for a clock cycle at least ( This resets the Flip Flops ),
then hold it high for the rest of the simulation.



Solution 2:

If the design is an HDL design, there may be another cause of
this problem of the outputs being undefined.  A bug exists
which prevents proper back-annotation in the timing simulation
netlist for designs which have been run through the MAP
optimizer, called OPTX.  In the HDL Editor, in the Synthesis
Options, there is an option to select an Optimization strategy.
The choices are BALANCE, AREA, SPEED, OFF.  If any of these
except OFF are chosen, MAP runs the OPTX optimize program on
the design.  Due to the renaming of nets in this process, the
design may not produce a correct timing simulation netlist, and
therefore you will see some or all of the outputs in the design
be unknown in timing simulation.  (Note that this problem only
affects the timing simulation netlist.	The actual physical
design file is unaffected, so if you were to download the
design to a device, it should operate properly.)

The problem lies in the NGM file, which enables the
back-annotated timing simulation netlist to correlate to the
original design.  Therefore, it is possible to work around this
problem by re-running NGDANNO from a command-line without the
NGM file.  NGDANNO is normally run after the place-and-route
phase.	To perform this workaround, follow the following steps:

1.  Place and route the design as usual through the Design
    Manager.

2.  Open up a DOS Prompt, and change to the current project
    directory.	Traverse the project directory hierarchy down
    through the XPROJ/VER/REV directory until you get to the
    appropriate REV directory where the most recent .NCD file
    is.  (The NCD file is the placed-and-routed design)

3.  Run the following from the DOS Prompt:

ngdanno -o no_ngm.nga <project_name>.ncd
ngd2edif no_ngm.nga

(This will create an EDIF file, called no_ngm.edn)

*Note:	<no_ngm> can be any name you wish for the output
netlist to be called.

4.  Invoke the Timing Simulator in Foundation as usual.

5.  Once inside the Simulator, select File -> Load Netlist,
    and choose the .EDN file created in Step 3.

6.  Simulate as usual.

By not using the NGM file in NGDANNO, not all of the original
netnames may be annotated to the simulation netlist.  What this
means is that you may not see all of your original signal
names in the simulator.  The design should still simulate,
however, and proper values should be seen on the pins at least,
and also on any internal signals whose names were not altered
by the OPTX program.


A second alternative to work around this problem is to not run
the OPTX program in MAP.  To disable this, select Optimize:Off
in the HDL Editor, Synthesis->Options.



End of Record #3219