Answers Database

F1.4, FPGA Express 2.0: Inverting Pin on HDL instantiation does not work


Record #3235

Product Family:  Software

Product Line:  Synopsys

Problem Title:
F1.4, FPGA Express 2.0: Inverting Pin on HDL instantiation does not work


Problem Description:
Keywords:  FPGA Express, 1.2, 2.0, instantiate, invert, <>

Urgency:  Standard

When instantiating a cell within HDL (VHDL or Verilog) to be compiled by
FPGA Express, if a user inverts the signal in the port map, the pin is renamed
in bus style.  For example

STARTUP U1	(.GSR(!reset));

would give a pin named GSR<0>.	This will cause connectivity problems with the
instantiated block.


Solution 1:

The workaround is to have an intermediate signal to invert the reset signal
before the pin assignment.  Example:

foo = !reset;
STARTUP U1    (.GSR(foo));



End of Record #3235