Answers Database

M1.4 Map - Timespec'ing RAMS (dualport) to FFS only covers SPO path.


Record #3243

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
M1.4 Map - Timespec'ing RAMS (dualport) to FFS only covers SPO path.


Problem Description:
When using the TIMEGRP constraint in a UCF to constrain the paths between the du
al port RAMs and connected flops, only the F LUTs get referenced in the PCF. Thi
s only covers the SPO (associated with the FLUT) but not the DPO (associated wit
h G LUT).




Notice the first TIMEGRP line contains only BEL "ram16d_spo", repeated
twice. The BEL's name "ram16d_spo" is based on the output SPO net. The
DPO net has the name "ram16d_dpo", so  the TIMEGRP line was changed
like so:

TIMEGRP "RAMS(ram16d*)" = BEL "ram16d_spo" BEL "ram16d_dpo" BEL "ram16d_spo" ;

This works. TRCE now controls both SPO and DPO.

(Oddly PERIOD constraint will cover this.)


Solution 1:

This issued has been fixed in the mapper so that the correct .pcf
constraints are written. This fix is included in the current M1.4 Core
Applications patch available from the Xilinx Download Area:

ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt14.zip



End of Record #3243