Answers Database

Foundation F1.4 Simulator, XC5200: Outputs are undefined in Timing Simulation


Record #3279

Product Family:  Software

Product Line:  Aldec

Problem Title:
Foundation F1.4 Simulator, XC5200: Outputs are undefined in Timing
Simulation



Problem Description:
Keywords:  undefined, initialize, unknown, simulate, GR, reset

Urgency:  Standard

When running a Timing Simulation of a 5K device in Foundation
1.4 the outputs of the simulation are undefined.


Solution 1:

The cause of this may be that the registers are not getting
initialized properly.  There is a signal called GR in the
simulation netlist which simulates the power-on global reset.
This GR signal must be toggled at the start of the simulation
in order to properly initialize the simulation.

To drive this GR signal:
Select Signal -- Add Signals. Then double click on the GR
signal. Now apply a stimulas to the signal and Toggle. Hold it
high for a clock cycle at least ( This resets the Flip Flops ),
then hold it low for the rest of the simulation.



End of Record #3279