Answers Database

M1, Timing, CPLD: What are negative setup times in CPLD Performance report?


Record #3302

Product Family:  Software

Product Line:  FPGA Core

Problem Title:
M1, Timing, CPLD: What are negative setup times in CPLD Performance
report?



Problem Description:
Keywords:  M1, Timing, CPLD, Negative, Setup time.

Urgency:   Standard

General Description:
After running M1 and creating a 'Post Layout Timing Report', in the timing repor
t (a.k.a. Performance Summary Report), there may be negative values for setup ti
mes such as below:

Setup to Clock at the Pad (tSU) 	  :	   -13.0ns (0 macrocell levels)
Data signal 'CS10' to TFF D input Pin at '&__A__55.D'
Clock pad 'R_W' 						  (Global Clock)


Negative setup time is the result of a clock signal that is slower than the tota
l delay and setup on the data input to the ff.	Normal (positive) setup time is
when the ff data must be stable before clock comes. The equation to calculate th
e time is:

Tsu=Tin+Tlogi+Tsui-Tgck   (pg 2-11:CPLD Databook:5/97)

In the case where setup time is negative, the data arrives at the ff, stays for
setup, then disappears before the clock comes. In the above equation, Tgck is la
rger than the sum of the rest, therefore there is a negative Tsu.

For more information on this or equations for other configurations, please see t
he ISP Application Guide and/or the Xilinx App note XAPP071 - Using the XC9500 T
iming Model.


Solution 1:

To resolve the timing problem, the data must be maintained on the input of the f
f until clock comes (Tgck). The negative Tsu is the additional time the data mus
t remain valid before the clock comes.



End of Record #3302