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SYNPLIFY: How to instantiate the STARTUP for a XC5200?


Record #3323

Product Family:  Software

Product Line:  Synplicity

Problem Title:
SYNPLIFY: How to instantiate the STARTUP for a XC5200?


Problem Description:
Keywords:  GR, synplify, xc5200, vhdl, verilog, startup

Urgency:   Standard

General Description:  The global reset in the 5200 uses dedicated
routing resources to reset ALL flip-flops in the device.  How to
to access the reset (GR) pin on the STARTUP block in HDL?


Solution 1:

// This will work for XC5200, though the reset signal on the startup
// block is labeled GR.  Synplify will map GSR signal name to GR in
// the netlist.

`include "/products/synplify.ver3_0/lib/xilinx/xc4000.v"

module use_gr (reset);
input reset;

// the signal reset initializes all registers using the
// global STARTUP signal
STARTUP U1 (.GSR (reset));

endmodule



Solution 2:

You can instantiate STARTUP cells by using the import library
supplied with Synplify. The Synplify Xilinx Macro Libraries contain
pre-defined black-boxes for the Xilinx macros so that you can manually
instantiate them into your design.

For VHDL based designs all one has to do is add the following 2 lines
in the VHDL and instantiate PULLUP/PULLDOWN components. Please look
in the $SYNPLICITY/lib/xilinx/xc4000.vhd on the WS or
C:/synplcty/lib/xilinx/xc4000.vhd on the PC for PULLUP/PULLDOWN
components and its port interface list.  For xc5200 VHDL designs,
use xc4000.vhd "black box" instantiation as an example.  A xc5200
library file does not exist, so use the xc4000 library.
	
	library xc4000;
	use xc4000.components.all;

For Verilog designs, just add the xc4000.v file in the source file list
along with the source design file. The xc4000.v file is also in the
$SYNPLICITY/lib/xilinx directory on the WS or C:\synplcty\lib\xilinx.
For xc5200 Verilog designs, use xc4000.v black box instantiation as
an example.



Solution 3:

-- This will work for XC5200, though the reset signal on the startup
-- block is labeled GR.  Synplify will map GSR signal name to GR in
-- the netlist.

library IEEE;
use IEEE.std_logic_1164.all;
library xc4000;
use xc4000.components.all;

entity use_gr is
   port (
	reset : in STD_LOGIC
	);
end use_gr;

architecture xilinx of use_gr is

begin

-- the signal reset initializes all registers using the
-- global STARTUP signal
U1 : STARTUP port map (GSR => reset);

end xilinx;



End of Record #3323