Answers Database
M1.3/1.4 TRACE: A DPRAM DPO to destination FROM:TO constraint is not analyzed
Record #3332
Product Family: Software
Product Line: Merged Core
Problem Title:
M1.3/1.4 TRACE: A DPRAM DPO to destination FROM:TO constraint is not
analyzed
Problem Description:
Keywords: Dual Port Ram, TIG, constraints, DPO, SPO
Urgency: Hot
A TNM attached to a DPRAM may not attach itself correctly
to the RAM if the SPO output is not connected. For example,
for the following path:
|--------|
| DPRAM |
| spo|---x
| | |----|
| dpo|-----------------|D Q|
| | |> |
|--------| |----|
tnm=myram tnm=myflop
This path would be picked up by a PERIOD constraint. However,
a constraint such as "TIMESPEC TS_IG=FROM:myram:TO:myflop:TIG;"
will not be recognized (path still in PERIOD constraint ).
Even if the constraint is not a TIG ( a normal FROM:TO, for
instance), it will still not be recognized (PERIOD will still
control it).
Solution 1:
This is actually a MAP bug, and it is fixed in a M1.4 patch
on the FTP site. Go to: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance
and download the appropriate "core" patch for your platform.
End of Record #3332
For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals! |