Answers Database

A1.4: What's new in A1.4 XSI


Record #3345

Problem Title:
A1.4: What's new in A1.4 XSI


Problem Description:

keywords: xsi,synopsys,unisim,roc,toc,startbuf,rocbuf,tocbuf
40125,osc4

urgency: standard

general description:

This is a short summary of the new features in
the A1.4 XSI software package


Solution 1:



In the A1.4 XSI Verilog flow with VerilogXL v2.5a, a new
pre-synthesis simulation flow is possible, even if the
Verilog code has cells instantiated from the XSI libraries.
The simulation library that make this possible is the
UNISIM libraries.

In the A1.4 XSI VHDL flow with a VHDL simulator, it is
possible to perform a pre-synthesis and post-synthesis
functional simulation before going into the M1 flow.  The
simulation library that makes this possilbe is the UNISIM
libraries.  Functional simulation in the A1.4 XSI VHDL flow
is possible, even if symbols from the XSI A1.4 library
are instantiated in the VHDL code.

The A1.4 XSI libraries include synthesis libraries for the
40125xv-1, 40125xv-2, and Spartan.

The A1.4 XSI HDL flows can now simuiate the GSR, GTS, STARTUP,
and oscillator devices, both in functional and timing
simulation.  Simulation of GSR, GTS, STARTUP, and
oscillators(e.g. OSC4) is made possible by the ROC,TOC,
STARTBUF,TOCBUF, & OSC4.

A new library in the A1.4 XSI flow is the UNISIM library.
The UNISIM library allows functional simulation of
Xilinx global nets(GSR/GTS), STARTUP, and oscillators.	The
UNISIM libraries support, XC3000, XC4000(including
Spartan), & XC5200.  When doing a functional simulation
in A1.4 with XSI, reference the HDL UNISIM library in
your HDL code and/or your HDL simulator.



End of Record #3345