Answers Database

M1.4 PAR - XC4000 design crashes after starting the Initial Timing Analysis.


Record #3396

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
M1.4 PAR - XC4000 design crashes after starting the Initial Timing
Analysis.



Problem Description:
See similar but different issue covered by Solution 3317.

There is a known map bug that will lead to a crash in PAR
during initial timing analysis. The problem is caused by
clock configurations where an internal signal drives a buffer
that in turn drives a clock buffer. Map correctly optimizes
the buffer out of the design but loses the connection to the
clock buffer. The driver-less clock buffer leads to a crash
in PAR.


Solution 1:

This problem can be avoided by placing a NOMERGE property
on the signal driving the clock buffer and re-mapping the
design. The following .ucf constraint will accomplish this:

  NET "net_name" KEEP ;

The map bug is scheduled to be fixed in the upcoming M1.5
release.



Solution 2:

This problem is fixed in the latest M1.4 Core Tools Patch available on the Xilin
x Download Area:

ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt14.zip



End of Record #3396