Answers Database

M1.4 Constraints: LOC'ing a PAD to an edge or multiple sites


Record #3470

Problem Title:
M1.4 Constraints: LOC'ing a PAD to an edge or multiple sites


Problem Description:
Keywords: edge, side, pin locking

Urgency: standard


How does one LOC a given PAD to a particular side of the
die?


Solution 1:

The syntax "L, R, T, B, TL, etc." is not supported for
PAD LOCs (they are for edge decoders and clocks). Therefore,
to LOC a PAD to any location on a given edge, you must
enumerate the list of IOB sites into the UCF or PCF file.
If you use the UCF file, you can create a list of locations
to LOC it to:

NET mysig LOC = P2, P3, P4, P5, P6, P7;

Unfortunately, MAP will not accept the wildcards in the
IOB site locations, so you cannot do: P?, P1?, P2?, P3? to
LOC to sites P1 through P39. You must explicity list the
sites.

However, you may use wildcards in the PCF on IOB sites. The
syntax is:

COMP "mynet" LOCATE = SITE "P?" SITE "P1?" SITE "P2?" SITE
"P3?" SITE "P40" SITE "P41" LEVEL 1;

This is preferably placed somewhere after the SCHEMATIC END;
statement in the PCF. The above example would LOC to any
pin from P1 to P41.
Take note that the above assumes the IOB name will be the
same as the PAD net, which may not be true if a BLKNM attribute
is placed on the PAD by the user (this is unusual). Also
realize that Xilinx normally does not recommend editing the
PCF file, as it is not a "user-friendly" syntax. Perform
edits to the PCF only if necessary.





End of Record #3470