Answers Database

SYNPLIFY: How does Synplify handle asynchronous set/reset flip-flops (DFFRS)?


Record #3486

Problem Title:
SYNPLIFY: How does Synplify handle asynchronous set/reset flip-flops
(DFFRS)?



Problem Description:
Keywords: synplify, dffrs

Urgency: Standard

General Description: How does Synplify handle asynchronous set/reset
flip-flops for Xilinx architectures?


Solution 1:

The xc3000/a, xc4000/e/ex/xl/xv, and xc5200 architectures do not
have an asynchronous set/reset flip-flop.  So, it is unadvisable
to descibe a register in the HDL code which the targeting
architecture can not support.  Xilinx does not recommend using
these types flip-flops.

The xc2000, xc7000, xc9500, and Virtex have primitives available
for these type of flip-flops.  The primitive FDCP maps to the
DFFRS.

Synplify will synthesize the generic DFFRS component because there
is no corresponding primitive to infer.  If this is the case, then
the HDL code needs to be modified to accomodate the targeting
architecture.

The xc4000/e/ex/xl family registers have an asynchronous set or
reset, but not both at the same time on the same register.

However, Synplicity does supply xc4000 XNF netlists for a DFFRS
constructed out of latches (LDCP_1).  The latches themselves are
constructed using cross-coupled gates.	These XNF netlists are
located in the C:\synplcty\lib\xilinx directory on the PC, and
$SYNPLICITY/lib/xilinx on the WS.



End of Record #3486