Answers Database

M1.4 Map - 5200: Map is not trimming global reset signals


Record #3525

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
M1.4 Map - 5200: Map is not trimming global reset signals


Problem Description:
For the Synopsys Verilog flow, the current methodology for Verilog design creati
on is to connect all register reset/preset signals to both the registers and STA
RTUP block so that functional simulation of the reset may be performed.  Upon im
plementation, Map should trim this signal connected to the STARTUP block however
 is not.  This redundant routing is obviously not desired.
For more details see CR_README in the data directory.


Solution 1:

A fix for this problem is included in the current M1.4 Core
Applications patch available from the Xilinx Download Area:

ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt14.zip



End of Record #3525