Answers Database

A1.4/F1.4 PAR - PAR introduces DRC error: "ERROR:x45dr - netcheck: Signal <net> is routed to the O pin of block <comp> on routing which is not available because the EC pin is using the Logic Zero option.


Record #3570

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
A1.4/F1.4 PAR - PAR introduces DRC error: "ERROR:x45dr - netcheck:
Signal <net> is routed to the O pin of block <comp> on routing which is not
available
because the EC pin is using the Logic Zero option.



Problem Description:
PAR appears to finish successfully, but DRC flags the following
error introduced during routing:

ERROR:x45dr - netcheck: Signal <net> is routed to the O pin of block <comp> on r
outing which is not available because the EC pin is using the Logic Zero option.


Solution 1:

A fix for this routing error is included in the current M1.4 Core
Applications patch available from the Xilinx Download Area:

ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt14.zip



End of Record #3570