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SYNPLIFY: How to use OSC5, OSC52, and CK_DIV cells for the XC5200 in HDL?


Record #3584

Problem Title:
SYNPLIFY: How to use OSC5, OSC52, and CK_DIV cells for the XC5200 in
HDL?



Problem Description:
Keywords: osc5, osc52, ck_div, synplify

Urgency: Standard

General Description: How to use OSC5, OSC52, and CLK_DIV components
for the XC5200 in HDL?

The OSC5, OSC52, and CK_DIV cells require the DIVIDE1_BY or the
DIVIDE2_BY attribute to specify appropriate clock division ratios.
You must use the DIVIDE1_BY attribute with the OSC1 output and the
DIVIDE2_BY attribute with the OSC2 output.  The OSC1 output facilitates
division ratios of 4, 16, 64, or 256.  The OSC2 output facilitates
division ratios of 2, 8, 32, 128, 1024, 4096, 16384, or 65536.	The
CK_DIV is not available if the OSC5 element is used, and vice-versa.


Solution 1:

module osc5_ex (A, Q);
input  [1:0] A;
output [1:0] Q;

reg [1:0] Q;
wire clk1_in, clk1_out;
wire clk2_in, clk2_out;

BUFG U0 (.I (clk1_in), .O (clk1_out));
BUFG U1 (.I (clk2_in), .O (clk2_out));
OSC5 U2 (.OSC1 (clk1_in), .OSC2 (clk2_in));

always @(posedge clk1_out)
begin
   Q[0] <= A[0];
end

always @(posedge clk2_out)
begin
   Q[1] <= A[1];
end

endmodule

module OSC5 (OSC1, OSC2) /* synthesis black_box
   xc_props="DIVIDE1_BY=4,DIVIDE2_BY=2" */;
output OSC1;
output OSC2;

endmodule

module BUFG (O, I) /* synthesis black_box */;
output	 O;
input	 I;

endmodule



Solution 2:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity osc5_ex is
    port (
	  A : in STD_LOGIC_VECTOR (1 downto 0);
	  Q : out STD_LOGIC_VECTOR (1 downto 0)
	);
end osc5_ex;

architecture xilinx of osc5_ex is

    attribute black_box : boolean;
    attribute xc_props: string;

    component OSC5
	port (
	      OSC1, OSC2 : out STD_LOGIC);
    end component;
    attribute xc_props of OSC5 : component is "DIVIDE1_BY=4,DIVIDE2_BY=2";
    attribute black_box of OSC5 : component is true;

    component BUFG
	port(
	     O : out STD_LOGIC;
	     I : in  STD_LOGIC);
    end component;
    attribute black_box of BUFG : component is true;

signal clk1_in, clk1_out : STD_LOGIC;
signal clk2_in, clk2_out : STD_LOGIC;

begin

U0: BUFG port map (I => clk1_in, O => clk1_out);
U1: BUFG port map (I => clk2_in, O => clk2_out);
U2: OSC5 port map (OSC1 => clk1_in, OSC2 => clk2_in);

process (clk1_out)
begin
   if (clk1_out'event and clk1_out = '1') then
       Q(0) <= A(0);
   end if;
end process;

process (clk2_out)
begin
   if (clk2_out'event and clk2_out = '1') then
       Q(1) <= A(1);
   end if;
end process;

end xilinx;



End of Record #3584