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Design Manager M1.4/M1.5: How to generate a VHDL/Verilog test fixture/testbench file


Record #3587

Product Family:  Software

Product Line:  M1 Graphical/General

Problem Title:
Design Manager M1.4/M1.5:  How to generate a VHDL/Verilog test
fixture/testbench file



Problem Description:
Keywords: Template Manager, Design Manager, VHDL, test bench, simulation templat
e

Urgency: Standard


How do you generate a VHDL/Verilog test fixture/testbench file ?


Solution 1:

In order to create a VHDL/Verilog test fixture/testbench file from
within the Design Manager (M1.5):

Utilize the Simulation Templates available from the Options dialog
(Design->Implement->Options)

1. Select the VHDL/Verilog simulator of choice from the drop-down menu
2. Click on Edit Template (VHDL/Verilog tab).
3. Select the option to "Generate Test Fixture/Testbench file"
4. Click OK to save
5. In the Options dialog, select "Produce Timing Simulation Data"
under Optional Targets.

By default, a time_sim(.tv or .tvhd) and time_sim.sdf file will be
created and copied into the root design directory.



Solution 2:

In order to create a VHDL/Verilog test fixture/testbench file from
within the Design Manager (M1.4):

1. Select Utilities->Template Manager->Edit->Interface->Simulation Data Options-
>Format: VHDL or Verilog
2. Click OK to save

Now create a new implementation template within the Template Manager
(Xilinx Solution 1227), specifying the following:

Program: ngd2vhdl
Options: -tb

or

Program: ngd2ver
Options: -tf

Back in the options dialog, be sure to select the newly created template
from within the Program Option Templates for Implementation.  In addition, selec
t "Produce Timing Simulation Data" under Optional Targets.




End of Record #3587