Answers Database

XC9500 JTAG: Troubleshooting hints for the Embedded micorprocessor ISP programming


Record #3652

Product Family:  Hardware

Product Line:  9500

Problem Title:
XC9500 JTAG: Troubleshooting hints for the Embedded micorprocessor ISP
programming



Problem Description:
Keywords: 9500, embedded, svf, xsvf, isp, micro, 8051, erase, program, fail

Urgency: Standard

General Description:

Tips for debugging problems associated with the embedded microprocessor ISP
programming for the XC9500 devices.


Solution 1:

Is the C-Code that is being used, provided by Xilinx? If it
is provided by someone else, there may be problems with the
code itself. For example, the most common mistake is clocking
one time too many in the SHIFT-IR/DR states. The last bit of an
n bit instruction/data gets shofted in on the transition from
the SHIFT state to UPDATE state.



Solution 2:

If the code is provided by Xilinx, then the correct port
information for the microprocessor being used must be entered in the
ports.c file and the I/Os must be setup properly.



Solution 3:

Can the processor wait for 1.3 seconds for the ERASE cycle and
160 micro seconds for PROGRAM? The 9500 devices take 1.3
seconds to ERASE and 160 micro seconds to program and those times
are embedded in the SVF/XSVF files.

A wait time linked to TCK is not recommended. If you are using
a processor such as the 8051, then you should use its internal
timer.

If you have mulitple parts in the chain, then the SVF files
for all the parts should be concatenated to form one file.

If the ERASE operation keeps failing continually, bumping up the
ERASE times in the SVF file to 3 seconds should be enough.

Note: If you created the SVF files using the EZTag software,
then the ERASE times should be bumped up to 1.3 seconds. The
default time used by EZTag is 0.5 seconds, which is incorrect.

For a more detailed description of the ERASE operation failing
look at http://www.xilinx.com/techdocs/3653.htm.



End of Record #3652